BEE2 Information
Background
The BEE2 system is designed to be a modular, scalable FPGA-based computing platform with a software
design methodology that targets a wide range of high-performance applications, such as:
- Real-time radio telescope signal processing
- Cognitive radio systems
- Hyperspectral image processing
- E & M antenna simulation
- Bioinformatics sequence matching
- Simulation of large-scale, ad-hoc and traditional networks
- ECAD tool acceleration
- Scientific computing
- Computer architecture emulation
The modular system architecture can not only provide orders of magnitude reduction in overall
cost and design time, but it also closely tracks the early adoption of state-of-the-art IC fabrication
by FPGA vendors. Users of the BEE2 have the freedom to choose the appropriate number of computational
modules needed to tackle the application at hand, and to rapidly reconfigure to switch to a different
application.
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Module Information
The BEE2 is a general purpose processing module based on five, high-performance Xilinx FPGAs (Virtex II Pro 70).
In addition to the large amount of processing fabric provided by the FPGAs, the BEE2 also provides
up to 20GB of high-speed, DDR2 DRAM memory. Each of the five FPGAs has four independent channels to
DDR2 DIMMs which provides very high memory bandwidth. Finally, the FPGAs on the BEE2 are highly
connected with both high-speed, serial and parallel links.
The FPGAs are laid out in a star
topology with four user FPGAs in a ring and one control FPGA connected to each user. The user FPGAs
each have four independent high speed serial channels (4 bonded MGTs) which are capable of transfering data at
10Gbps through CX4 connectors (both copper and fiber). The user FPGA ring consists of parallel
connections of 138 high-speed LVCMOS traces between the FPGAs which can run at a maximum of 400Mbps.
The control FPGA has two high-speed serial channels, 64 LVCMOS traces to each user FPGA, and connections
to common peripherals such as 10/100 ethernet, USB 1.1, RS232 serial, DVI, and GPIOs.
Detailed information about the BEE2 module, including its architecture, links to data sheets,
BOM, and source code can be found here:
http://bee2.eecs.berkeley.edu/module/
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Presentations:
- 2004 International SKA meeting poster (pdf)
- A Case for High End Reconfigurable Computing (pdf)
Whitepapers:
- BEE2: A Multi-Purpose Computing Platform for Radio Telescope Signal Processing Applications
(pdf)
Papers:
- BEE2: A High-End Reconfigurable Computing System (pdf)
- Physical Design and Implementation of BEE2: A High End Reconfigurable Computer (MS Report)
(pdf)
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(Last Updated: Feb 22, 2008)