# BEE2 board specification

# Xilinx XC2VP70 Control FPGA

# Last Changes:
# Pierre-Yves Droz	5/20/2004 1:48PM

# Best viewed with tab_length=6

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# Infiniband ports
!! set infiniband_port ""
!! for {set i 0} {$i < 2} {incr i 1} {
!! 	set infiniband_port "${infiniband_port}	infiniband_${i}_tx_p	infiniband_${i}_tx_m	infiniband_${i}_rx_p	infiniband_${i}_rx_m"
!! }
# High speed Serial ATA ports
!! set hs_sata_port ""
!! for {set i 0} {$i < 2} {incr i 1} {
!! 	set hs_sata_port "${hs_sata_port}	hs_sata_top_${i}_tx_p	hs_sata_top_${i}_tx_m	hs_sata_top_${i}_rx_p	hs_sata_top_${i}_rx_m"
!! }
!! for {set i 0} {$i < 10} {incr i 1} {
!! 	set hs_sata_port "${hs_sata_port}	hs_sata_bottom_${i}_tx_p	hs_sata_bottom_${i}_tx_m	hs_sata_bottom_${i}_rx_p	hs_sata_bottom_${i}_rx_m"
!! }

# Selectmap busses
!! set selectmap_port "cclk_fpga"
!! foreach fpga $usr_fpgas {
!! 	set selectmap_port "${selectmap_port}	done_${fpga}	prog_${fpga}_	init_${fpga}_	cs_${fpga}_	data_${fpga}_d	rdwr_${fpga}_"
!! }

# LVCMOS ports
!! set lvcmos_port ""
!! foreach fpga $usr_fpgas {
!! 	set lvcmos_port "${lvcmos_port}	lvcmos_down_${fpga}_d"
!! }

# FPGA VCCOs
!! set vccos ""
!! for {set i 0} {$i < 8} {incr i 1} {
!! 	set vccos "${vccos}	vcco_bk${i}_b"
!! }

# FPGA DCI resistors
!! set vrs ""
!! foreach i [list 0 1 2 3 4 5 6 7] {
!! 	set vrs "${vrs}	vrn_bk${i}	vrp_bk${i}"
!! }

# FPGA Vrefs
!! set vrefs ""
!! foreach i [list 2 3 6 7] {
!! 	set vrefs "${vrefs}	bk${i}_vref"
!! }

# Memory modules
!! set mems ""
!! for {set i 1} {$i <= 4} {incr i 1} {
!! 	set mems "${mems}		membk${i}_s_	membk${i}_odt	membk${i}_ck_p	membk${i}_ck_m	membk${i}_cke	membk${i}_div_out	membk${i}_div_in	membk${i}_ras_	membk${i}_cas_	membk${i}_we_	membk${i}_ba	membk${i}_a	membk${i}_dq	membk${i}_dqs	membk${i}_dm	membk${i}_cb	membk${i}_reset_"
!! }

# Control FPGA
add_blk	ctrlfpga	XCV2P70_ctrl	dvi_ddc_18_clk	dvi_ddc_18_data	dvi_data	dvi_idck_p	dvi_idck_m	dvi_hsync	dvi_vsync	dvi_de	panel_buf_oe_	panel_buf_dir	usb_data_buf_oe_	usb_data_buf_dir	usb_data	usb_intrq	usb_a0	usb_cs_	usb_rd_	usb_wr_	usb_rst_	phy_reset_	phy_slew	phy_mdio	phy_mdc	phy_rxd	phy_rx_dv	phy_rx_clk	phy_tx_clk	phy_rx_er	phy_tx_er	phy_tx_en	phy_txd	phy_col	phy_crs	phy_mdint_	sysclk_p	sysclk_m	usrclk_p	usrclk_m	sysclk_en_	usrclk_en_	mpce_	mpwe_	mpoe_	mpirq	mpa	mpd	mclk	tdi	tdo	tms	tck	prog_	init_	cfgmode0_b	cfgmode1_b	cfgmode2_b	done	cclk	dxp	dxn	${selectmap_port}	smb_clk	smb_data	smb_alert_	usrclk_sclk	usrclk_data	usrclk_strobe	rs232_rx	rs232_tx	rs232_cts	rs232_rts	avccauxtx_top	avccauxrx_top	vttx_top	vtrx_top	gnda_top	avccauxtx_bottom	avccauxrx_bottom	vttx_bottom	vtrx_bottom	gnda_bottom	brefclk_top_p	brefclk_top_m	brefclk2_top_p	brefclk2_top_m	brefclk_bottom_p	brefclk_bottom_m	${infiniband_port}	${hs_sata_port}	${lvcmos_port}	period_int	reset_	mem_scl	mem_sda	${mems}	gpleds	panel_18_in	panel_18_out	hswap_en	vbatt	vccint	vccaux	${vccos}	${vrs}	${vrefs}	powergnd
def_param_blk	ctrlfpga	package	1704BGA	part_number	2V2P70	manufacturer	Xilinx	www	http://direct.xilinx.com/bvdocs/publications/ds083.pdf	description	FPGA	distributor	Xilinx	order_number	N/A	availability	see with Xilinx

# System clock input
add_con	in	ctrlfpga	sysclk_p	1	sysclk_ctrlfpga_p	0
add_con	in	ctrlfpga	sysclk_m	1	sysclk_ctrlfpga_m	0

# User clock input
add_con	in	ctrlfpga	usrclk_p	1	usrclk_ctrlfpga_p	0
add_con	in	ctrlfpga	usrclk_m	1	usrclk_ctrlfpga_m	0

# Clock enable
add_con	out	ctrlfpga	usrclk_en_	1	usrclk_en_		0
add_con	out	ctrlfpga	sysclk_en_	1	sysclk_en_		0

# Reset
add_net	ctrlfpga_reset_	1
add_con	in	ctrlfpga	reset_	1	ctrlfpga_reset_	0
add_term	drop	ctrlfpga	reset_	VCC1_8	[res_type 1K 1%]	1	[res 1K 1%]
add_term	drop	ctrlfpga	reset_	GND		[cap_type 10uF tantalum]	1	[cap 10uF tantalum]

add_term	drop	ctrlfpga	reset_	GND		HDR_2	1	[hdr SW_Reset_PB 1x2]
add_term	drop	ctrlfpga	reset_	GND		[sw_type SW_Reset]	1	[sw SW_Reset]

# Port to the ethernet phy
add_con	out	ctrlfpga	phy_reset_	1	phy_reset_	0
add_con	out	ctrlfpga	phy_slew	2	phy_slew	0:1
add_con	bidir	ctrlfpga	phy_mdio	1	phy_mdio	0
add_con	out	ctrlfpga	phy_mdc	1	phy_mdc	0
add_con	in	ctrlfpga	phy_rxd	4	phy_rxd	0:3
add_con	in	ctrlfpga	phy_rx_dv	1	phy_rx_dv	0
add_con	in	ctrlfpga	phy_rx_clk	1	phy_rx_clk	0
add_con	in	ctrlfpga	phy_tx_clk	1	phy_tx_clk	0
add_con	in	ctrlfpga	phy_rx_er	1	phy_rx_er	0
add_con	out	ctrlfpga	phy_tx_er	1	phy_tx_er	0
add_con	out	ctrlfpga	phy_tx_en	1	phy_tx_en	0
add_con	out	ctrlfpga	phy_txd	4	phy_txd	0:3
add_con	in	ctrlfpga	phy_col	1	phy_col	0
add_con	in	ctrlfpga	phy_crs	1	phy_crs	0
add_con	bidir	ctrlfpga	phy_mdint_	1	phy_mdint_	0

# Access port to the compact flash
add_con	out	ctrlfpga	mpce_		1	cfg_mpce_		0	
add_con	out	ctrlfpga	mpwe_		1	cfg_mpwe_		0	
add_con	out	ctrlfpga	mpoe_		1	cfg_mpoe_		0	
add_con	in	ctrlfpga	mpirq		1	cfg_mpirq		0	
add_con	out	ctrlfpga	mpa		7	cfg_mpa		0:6	0:6	
add_con	bidir	ctrlfpga	mpd		8	cfg_mpd		0:7	0:7	

add_con	in	ctrlfpga	mclk		1	systemace_clk	0

# JTAG configuration port
add_con	in	ctrlfpga	tdi	1	cfg_jtag_systemace_2_ctrlfpga	0
add_con	out	ctrlfpga	tdo	1	cfg_jtag_ctrlfpga_2_jmp		0
add_con	in	ctrlfpga	tck	1	cfg_jtag_tck			0
add_con	in	ctrlfpga	tms	1	cfg_jtag_tms			0

# Configuration pins
add_con	bidir	ctrlfpga	prog_	1	cfg_prog_ctrlfpga_	0
add_con	bidir	ctrlfpga	init_	1	cfg_init_ctrlfpga_	0

add_term	drop	ctrlfpga	prog_	GND		[sw_type CTRL_PROG]	1	[sw CTRL_PROG]
add_term	drop	ctrlfpga	prog_	GND		[cap_type 100nF ceramic]	1	[cap 100nF ceramic]
add_term	drop	ctrlfpga	prog_	GND		HDR_2	1	[hdr CTRL_PROG_PB 1x2]

# Configuration mode - We use Select map to let access to the Icap - M2M1M0 is 110 for slave selectmap
add_blk	ctrlfpga_cfgmode_hdr	HDR_2X3_CFGMODE	cfgmode0	cfgmode1	cfgmode2	cfgmode0_p	cfgmode1_p	cfgmode2_p
def_param_blk	ctrlfpga_cfgmode_hdr	[hdr CTRLFPGA_MODE 2x3]

add_net	ctrlfpga_cfgmode0	1
add_con	in	ctrlfpga	cfgmode0_b	1	ctrlfpga_cfgmode0	0
!! add_pulldown ctrlfpga_cfgmode0
add_con	out	ctrlfpga_cfgmode_hdr	cfgmode0	1	ctrlfpga_cfgmode0	0
add_con	in	ctrlfpga_cfgmode_hdr	cfgmode0_p	1	VCC2_5		0

add_net	ctrlfpga_cfgmode1	1
add_con	in	ctrlfpga	cfgmode1_b	1	ctrlfpga_cfgmode1	0
!! add_pulldown ctrlfpga_cfgmode1
add_con	out	ctrlfpga_cfgmode_hdr	cfgmode1	1	ctrlfpga_cfgmode1	0
add_con	in	ctrlfpga_cfgmode_hdr	cfgmode1_p	1	VCC2_5		0

add_net	ctrlfpga_cfgmode2	1
add_con	in	ctrlfpga	cfgmode2_b	1	ctrlfpga_cfgmode2	0
!! add_pulldown ctrlfpga_cfgmode2
add_con	out	ctrlfpga_cfgmode_hdr	cfgmode2	1	ctrlfpga_cfgmode2	0
add_con	in	ctrlfpga_cfgmode_hdr	cfgmode2_p	1	VCC2_5		0

# Selectmap busses for the other FPGAs
add_net	cfg_cclk_fpga	1
add_con	out	ctrlfpga	cclk_fpga	1	cfg_cclk_fpga	0	
!! add_lvcmos_25_term cfg_cclk_fpga 1 1
!! add_lvcmos_25_term cfg_cclk_fpga 1 2
!! add_lvcmos_25_term cfg_cclk_fpga 1 3
!! add_lvcmos_25_term cfg_cclk_fpga 1 4

!! foreach fpga $usr_fpgas {

add_net	cfg_done_${fpga}	1
add_net	cfg_prog_${fpga}_	1
add_net	cfg_init_${fpga}_	1
add_net	cfg_cs_${fpga}_	1
add_net	cfg_data_${fpga}	8
add_net	cfg_rdwr_${fpga}_	1

add_con	in	ctrlfpga	done_${fpga}	1	cfg_done_${fpga}	0
add_con	bidir	ctrlfpga	prog_${fpga}_	1	cfg_prog_${fpga}_	0
add_con	bidir	ctrlfpga	init_${fpga}_	1	cfg_init_${fpga}_	0
add_con	out	ctrlfpga	cs_${fpga}_		1	cfg_cs_${fpga}_	0
add_con	out	ctrlfpga	data_${fpga}_d	8	cfg_data_${fpga}	0:7	
add_con	out	ctrlfpga	rdwr_${fpga}_	1	cfg_rdwr_${fpga}_	0	

!! add_pullup_25 cfg_prog_${fpga}_
!! add_pullup_25 cfg_init_${fpga}_
!! add_pullup_25 cfg_cs_${fpga}_
!! }

# Cclk
add_net	ctrlfpga_cclk	1
add_con	bidir	ctrlfpga	cclk	1	ctrlfpga_cclk	0
!! add_pulldown	ctrlfpga_cclk

# Done led
add_net	cfgdone_ctrlfpga	1
add_con	out	ctrlfpga	done	1	cfgdone_ctrlfpga	0
add_term	drop	ctrlfpga	done	VCC2_5	[res_type 511R 1%]	1	[res 511R 1%]

add_net	cfgdone_ctrlfpga_cat	1

add_blk	ctrlfpga_doneled	LED	a	c
def_param_blk	ctrlfpga_doneled	package	0603	part_number	PG1111C-TR	manufacturer	Panasonic	www	http://rocky.digikey.com/WebLib/Stanley/AA1111C.pdf	description	LED GREEN 0603 SMD	distributor	Digikey	order_number	404-1004-1-ND	availability	available

add_con	pwr	ctrlfpga_doneled	a	1	VCC3_3		0
add_con	pwr	ctrlfpga_doneled	c	1	cfgdone_ctrlfpga_cat	0

add_term	serial	ctrlfpga_doneled	a	[res_type 511R 1%]	1	[res 511R 1%]

add_blk	transistor_ctrlfpga_done	BSS138	g	d	s
def_param_blk	transistor_ctrlfpga_done	package	SOT23	part_number	BSS138TA	manufacturer	Zetex	www	http://www.zetex.com/3.0/pdf/BSS138.pdf	description	MOSFET N-CHAN 50V 200MA SOT-23	distributor	Digikey	order_number	BSS138ZXCT-ND	availability	available
add_con	analog	transistor_ctrlfpga_done	s	1	GND				0
add_con	analog	transistor_ctrlfpga_done	d	1	cfgdone_ctrlfpga_cat		0
add_con	analog	transistor_ctrlfpga_done	g	1	cfgdone_ctrlfpga		0

# Temperature sensor
add_con	analog	ctrlfpga	dxp	1	temp_ctrlfpga_dx_p	0
add_con	analog	ctrlfpga	dxn	1	temp_ctrlfpga_dx_m	0

# Periodic interrupt signal
add_net	ctrlfpga_18_period_int	1
add_con	in	ctrlfpga	period_int	1	ctrlfpga_18_period_int	0

# Port to the USB host controller
add_net	usb_18_data		8
add_net	usb_18_intrq	1
add_net	usb_18_a0		1
add_net	usb_18_cs_		1
add_net	usb_18_rd_		1
add_net	usb_18_wr_		1
add_net	usb_18_rst_		1

add_con	bidir	ctrlfpga	usb_data		8	usb_18_data		0:7
add_con	bidir	ctrlfpga	usb_intrq		1	usb_18_intrq	0
add_con	bidir	ctrlfpga	usb_a0		1	usb_18_a0		0
add_con	bidir	ctrlfpga	usb_cs_		1	usb_18_cs_		0
add_con	bidir	ctrlfpga	usb_rd_		1	usb_18_rd_		0
add_con	bidir	ctrlfpga	usb_wr_		1	usb_18_wr_		0
add_con	bidir	ctrlfpga	usb_rst_		1	usb_18_rst_		0
!! add_pullup_18	usb_18_rst_

# SMB
add_net	smb_18_clk		1
add_net	smb_18_data		1
add_net	smb_18_alert_	1

add_con	out	ctrlfpga	smb_clk		1	smb_18_clk		0
add_con	bidir	ctrlfpga	smb_data		1	smb_18_data		0
add_con	in	ctrlfpga	smb_alert_		1	smb_18_alert_	0

# User clock configuration bus
add_net	usrclk_18_sclk		1
add_net	usrclk_18_data		1
add_net	usrclk_18_strobe		1

add_con	out	ctrlfpga	usrclk_sclk		1	usrclk_18_sclk		0
add_con	out	ctrlfpga	usrclk_data		1	usrclk_18_data		0
add_con	out	ctrlfpga	usrclk_strobe	1	usrclk_18_strobe		0

# Connector to the panel
add_blk	panel_con	HDR_2X8_PANEL	data	ctrl	vcclogic	vcc5v	powergnd
def_param_blk	panel_con	[hdr PANEL 2x8]

add_net	panel_33_out	8
add_net	panel_33_in		5

add_con	bidir	panel_con	data		8	panel_33_out	0:7
add_con	bidir	panel_con	ctrl		5	panel_33_in		0:4

add_con	pwr	panel_con	vcc5v		1	VCC5			0
add_con	pwr	panel_con	vcclogic	1	VCC3_3		0
add_con	gnd	panel_con	powergnd	1	GND			0

add_net	panel_18_out	8
add_net	panel_18_in		5

add_con	in	ctrlfpga	panel_18_in		5	panel_18_in		0:4
add_con	out	ctrlfpga	panel_18_out	8	panel_18_out	0:7

# Logic level translator 1.8V <-> 3.3V unidirectional
add_blk	misc_buf_unidir	74VCX163245	a0	a1	a2	a3	a4	a5	a6	a7	a8	a9	a10	a11	a12	a13	a14	a15	b0	b1	b2	b3	b4	b5	b6	b7	b8	b9	b10	b11	b12	b13	b14	b15	oe1_	oe2_	dir1	dir2	vcca	vccb	powergnd	
def_param_blk	misc_buf_unidir	package	48TSSOP	part_number	74VCX163245MTD	manufacturer	Fairchild	www	http://www.fairchildsemi.com/ds/74/74VCX163245.pdf	description	LOGIC LEVEL TRANSLATOR	distributor	Arrow	order_number	N/A	availability	no stock

add_con	in	misc_buf_unidir	b0			1	usb_18_a0			0
add_con	out	misc_buf_unidir	a0			1	usb_33_a0			0

add_con	in	misc_buf_unidir	b1			1	usb_18_cs_			0
add_con	out	misc_buf_unidir	a1			1	usb_33_cs_			0

add_con	in	misc_buf_unidir	b2			1	usb_18_rd_			0
add_con	out	misc_buf_unidir	a2			1	usb_33_rd_			0

add_con	in	misc_buf_unidir	b3			1	usb_18_wr_			0
add_con	out	misc_buf_unidir	a3			1	usb_33_wr_			0

add_con	in	misc_buf_unidir	b4			1	usb_18_rst_			0
add_con	out	misc_buf_unidir	a4			1	usb_33_rst_			0

add_con	in	misc_buf_unidir	b5			1	usrclk_18_data		0
add_con	out	misc_buf_unidir	a5			1	usrclk_33_data		0

add_con	in	misc_buf_unidir	b6			1	usrclk_18_sclk		0
add_con	out	misc_buf_unidir	a6			1	usrclk_33_sclk		0

add_con	in	misc_buf_unidir	b7			1	usrclk_18_strobe		0
add_con	out	misc_buf_unidir	a7			1	usrclk_33_strobe		0

add_con	in	misc_buf_unidir	oe1_			1	GND				0
add_con	in	misc_buf_unidir	dir1			1	GND				0

add_con	out	misc_buf_unidir	b8			1	ctrlfpga_18_period_int	0
add_con	in	misc_buf_unidir	a8			1	ctrlfpga_33_period_int	0

add_con	out	misc_buf_unidir	b9			1	smb_18_alert_		0
add_con	in	misc_buf_unidir	a9			1	smb_33_alert_		0

add_con	out	misc_buf_unidir	b10			1	usb_18_intrq		0
add_con	in	misc_buf_unidir	a10			1	usb_33_intrq		0

add_con	out	misc_buf_unidir	b11			1	panel_18_in			0
add_con	in	misc_buf_unidir	a11			1	panel_33_in			0

add_con	out	misc_buf_unidir	b12			1	panel_18_in			1
add_con	in	misc_buf_unidir	a12			1	panel_33_in			1

add_con	out	misc_buf_unidir	b13			1	panel_18_in			2
add_con	in	misc_buf_unidir	a13			1	panel_33_in			2

add_con	out	misc_buf_unidir	b14			1	panel_18_in			3
add_con	in	misc_buf_unidir	a14			1	panel_33_in			3

add_con	out	misc_buf_unidir	b15			1	panel_18_in			4
add_con	in	misc_buf_unidir	a15			1	panel_33_in			4

add_con	in	misc_buf_unidir		oe2_			1	GND			0
add_con	in	misc_buf_unidir		dir2			1	VCC1_8		0

add_con	pwr	misc_buf_unidir	vcca			2	VCC3_3			0
!! add_bypass_hspeed_33 misc_buf_unidir 0
!! add_bypass_hspeed_33 misc_buf_unidir 1
!! add_bypass_bulk_33   misc_buf_unidir 0

add_con	pwr	misc_buf_unidir	vccb			2	VCC1_8			0
!! add_bypass_hspeed_18 misc_buf_unidir 0
!! add_bypass_hspeed_18 misc_buf_unidir 1
!! add_bypass_bulk_18   misc_buf_unidir 0

add_con	gnd	misc_buf_unidir	powergnd		8	GND				0

# Logic level translator 1.8V <-> 3.3V bidirectional
add_blk	misc_buf_bidir	74VCX163245	a0	a1	a2	a3	a4	a5	a6	a7	a8	a9	a10	a11	a12	a13	a14	a15	b0	b1	b2	b3	b4	b5	b6	b7	b8	b9	b10	b11	b12	b13	b14	b15	oe1_	oe2_	dir1	dir2	vcca	vccb	powergnd	
def_param_blk	misc_buf_bidir	package	48TSSOP	part_number	74VCX163245MTD	manufacturer	Fairchild	www	http://www.fairchildsemi.com/ds/74/74VCX163245.pdf	description	LOGIC LEVEL TRANSLATOR	distributor	Arrow	order_number	N/A	availability	no stock

add_con	bidir	misc_buf_bidir	b0			1	usb_18_data			0
add_con	bidir	misc_buf_bidir	a0			1	usb_33_data			0

add_con	bidir	misc_buf_bidir	b1			1	usb_18_data			1
add_con	bidir	misc_buf_bidir	a1			1	usb_33_data			1

add_con	bidir	misc_buf_bidir	b2			1	usb_18_data			2
add_con	bidir	misc_buf_bidir	a2			1	usb_33_data			2

add_con	bidir	misc_buf_bidir	b3			1	usb_18_data			3
add_con	bidir	misc_buf_bidir	a3			1	usb_33_data			3

add_con	bidir	misc_buf_bidir	b4			1	usb_18_data			4
add_con	bidir	misc_buf_bidir	a4			1	usb_33_data			4

add_con	bidir	misc_buf_bidir	b5			1	usb_18_data			5
add_con	bidir	misc_buf_bidir	a5			1	usb_33_data			5

add_con	bidir	misc_buf_bidir	b6			1	usb_18_data			6
add_con	bidir	misc_buf_bidir	a6			1	usb_33_data			6

add_con	bidir	misc_buf_bidir	b7			1	usb_18_data			7
add_con	bidir	misc_buf_bidir	a7			1	usb_33_data			7

add_net	usb_data_buf_oe_	1
add_net	usb_data_buf_dir	1
add_con	in	misc_buf_bidir	oe1_			1	usb_data_buf_oe_	0
add_con	in	misc_buf_bidir	dir1			1	usb_data_buf_dir	0
add_con	out	ctrlfpga	usb_data_buf_oe_	1	usb_data_buf_oe_	0
add_con	out	ctrlfpga	usb_data_buf_dir	1	usb_data_buf_dir	0
!! add_pullup_18 usb_data_buf_oe_
!! add_pullup_18 usb_data_buf_dir

add_con	in	misc_buf_bidir	b8			1	panel_18_out		0
add_con	out	misc_buf_bidir	a8			1	panel_33_out		0

add_con	in	misc_buf_bidir	b9			1	panel_18_out		1
add_con	out	misc_buf_bidir	a9			1	panel_33_out		1

add_con	in	misc_buf_bidir	b10			1	panel_18_out		2
add_con	out	misc_buf_bidir	a10			1	panel_33_out		2

add_con	in	misc_buf_bidir	b11			1	panel_18_out		3
add_con	out	misc_buf_bidir	a11			1	panel_33_out		3

add_con	in	misc_buf_bidir	b12			1	panel_18_out		4
add_con	out	misc_buf_bidir	a12			1	panel_33_out		4

add_con	in	misc_buf_bidir	b13			1	panel_18_out		5
add_con	out	misc_buf_bidir	a13			1	panel_33_out		5

add_con	in	misc_buf_bidir	b14			1	panel_18_out		6
add_con	out	misc_buf_bidir	a14			1	panel_33_out		6

add_con	in	misc_buf_bidir	b15			1	panel_18_out		7
add_con	out	misc_buf_bidir	a15			1	panel_33_out		7

add_net	panel_buf_oe_	1
add_net	panel_buf_dir	1
add_con	in	misc_buf_bidir	oe2_			1	panel_buf_oe_	0
add_con	in	misc_buf_bidir	dir2			1	panel_buf_dir	0
add_con	out	ctrlfpga	panel_buf_oe_	1	panel_buf_oe_	0
add_con	out	ctrlfpga	panel_buf_dir	1	panel_buf_dir	0
!! add_pullup_18 panel_buf_oe_
!! add_pullup_18 panel_buf_dir

add_con	pwr	misc_buf_bidir	vcca			2	VCC3_3			0
!! add_bypass_hspeed_33 misc_buf_bidir 0
!! add_bypass_hspeed_33 misc_buf_bidir 1
!! add_bypass_bulk_33   misc_buf_bidir 0

add_con	pwr	misc_buf_bidir	vccb			2	VCC1_8			0
!! add_bypass_hspeed_18 misc_buf_bidir 0
!! add_bypass_hspeed_18 misc_buf_bidir 1
!! add_bypass_bulk_18   misc_buf_bidir 0

add_con	gnd	misc_buf_bidir	powergnd		8	GND				0

# Logic level translator 1.8V <-> 3.3V bidirectional opendrain
add_blk	misc_buf_bidir_od	GTL2002	s1	s2	d1	d2	sref	gref	dref	powergnd
def_param_blk	misc_buf_bidir_od	package	8SO	part_number	GTL2002D	manufacturer	Phillips	www	http://www.semiconductors.philips.com/acrobat/datasheets/GTL2002_2.pdf	description	LOGIC LEVEL TRANSLATOR	distributor	Arrow	order_number	N/A	availability	available

add_con	bidir		misc_buf_bidir_od	s1	1	smb_18_data	0
add_con	bidir		misc_buf_bidir_od	d1	1	smb_33_data	0
!! add_pullup_18	smb_18_data

add_con	bidir		misc_buf_bidir_od	s2	1	smb_18_clk	0
add_con	bidir		misc_buf_bidir_od	d2	1	smb_33_clk	0
!! add_pullup_18	smb_18_clk

add_net	misc_buf_bidir_od_ref	1
add_con	analog	misc_buf_bidir_od	gref	1	misc_buf_bidir_od_ref	0
add_con	analog	misc_buf_bidir_od	dref	1	misc_buf_bidir_od_ref	0
add_term	net		misc_buf_bidir_od_ref	VCC3_3	misc_buf_bidir_od_ref_pullup	[res_type 200K 1%]		1	1	[res 200K 1%]
add_term	net		misc_buf_bidir_od_ref	GND		misc_buf_bidir_od_ref_bypass	[cap_type 100nF ceramic]	1	1	[cap 100nF ceramic]

add_con	analog	misc_buf_bidir_od	sref	1	VCC1_8	0
!! add_bypass_hspeed_18 misc_buf_bidir_od

add_con	gnd		misc_buf_bidir_od	powergnd	1	GND	0

# RS232 Interface
add_con	in	ctrlfpga	rs232_rx	1	rs232_rx	0
add_con	out	ctrlfpga	rs232_tx	1	rs232_tx	0
add_con	in	ctrlfpga	rs232_cts	1	rs232_cts	0
add_con	out	ctrlfpga	rs232_rts	1	rs232_rts	0

# DVI Interface
add_con	out	ctrlfpga	dvi_data	12	dvi_data	0:11
add_con	out	ctrlfpga	dvi_idck_p	1	dvi_idck_p	0
add_con	out	ctrlfpga	dvi_idck_m	1	dvi_idck_m	0
add_con	out	ctrlfpga	dvi_hsync	1	dvi_hsync	0
add_con	out	ctrlfpga	dvi_vsync	1	dvi_vsync	0
add_con	out	ctrlfpga	dvi_de	1	dvi_de	0

# DVI Data channel
add_con	out	ctrlfpga	dvi_ddc_18_data	1	dvi_ddc_18_data	0
add_con	out	ctrlfpga	dvi_ddc_18_clk	1	dvi_ddc_18_clk	0

# MGTs Power
!! 	foreach side [list top bottom] {
add_con	pwr	ctrlfpga	avccauxtx_${side}	10	avccauxtx_ctrlfpga_${side}	0:9
add_con	pwr	ctrlfpga	avccauxrx_${side}	10	avccauxrx_ctrlfpga_${side}	0:9
add_con	pwr	ctrlfpga	vttx_${side}	10	vttx_ctrlfpga_${side}	0:9
add_con	pwr	ctrlfpga	vtrx_${side}	10	vtrx_ctrlfpga_${side}	0:9

add_con	gnd	ctrlfpga	gnda_${side}	10	MGT_GND_ctrlfpga_${side}	0
!! 	}

# MGTs Clocks
add_con	in	ctrlfpga	brefclk_top_p	1	mgt_ctrlfpga_top_clk1_p			0
add_con	in	ctrlfpga	brefclk_top_m	1	mgt_ctrlfpga_top_clk1_m			0
add_con	in	ctrlfpga	brefclk2_top_p	1	mgt_ctrlfpga_top_clk2_p			0
add_con	in	ctrlfpga	brefclk2_top_m	1	mgt_ctrlfpga_top_clk2_m			0
add_con	in	ctrlfpga	brefclk_bottom_p	1	mgt_ctrlfpga_bottom_clk1_p		0
add_con	in	ctrlfpga	brefclk_bottom_m	1	mgt_ctrlfpga_bottom_clk1_m		0

# MGTs infiniband signals
	# Differential via structures

!! for {set index 0} {$index < 2} {incr index 1} {
add_con	out	ctrlfpga	infiniband_${index}_tx_p	4	infiniband_ctrlfpga_${index}_tx_p	0:3
add_con	out	ctrlfpga	infiniband_${index}_tx_m	4	infiniband_ctrlfpga_${index}_tx_m	0:3
add_con	in	ctrlfpga	infiniband_${index}_rx_p	4	infiniband_ctrlfpga_${index}_rx_p	0:3
add_con	in	ctrlfpga	infiniband_${index}_rx_m	4	infiniband_ctrlfpga_${index}_rx_m	0:3

!! 	foreach dir [list rx tx] {
!! 		for {set i 0} {$i < $put_via(ctrlfpga_${dir}_${index})} {incr i 1} {
!! 			for {set j 0} {$j < 4} {incr j 1} {
add_blk	diff_via_${dir}_ctrlfpga_${index}_${j}_${i}	DIFF_VIA	p	m	signalgnd
def_param_blk	diff_via_${dir}_ctrlfpga_${index}_${j}_${i}	virtual_part	true

add_con	analog	diff_via_${dir}_ctrlfpga_${index}_${j}_${i}	p		1	infiniband_ctrlfpga_${index}_${dir}_p	$j
add_con	analog	diff_via_${dir}_ctrlfpga_${index}_${j}_${i}	m		1	infiniband_ctrlfpga_${index}_${dir}_m	$j
add_con	gnd		diff_via_${dir}_ctrlfpga_${index}_${j}_${i}	signalgnd	2	GND	0

!!			}
!!		}
!! 	}
!! }

# MGTs High speed serial ATA signals
!! for {set index 0} {$index < 2} {incr index 1} {
add_con	out	ctrlfpga	hs_sata_top_${index}_tx_p	1	hs_sata_top_ctrlfpga_${index}_tx_p	0
add_con	out	ctrlfpga	hs_sata_top_${index}_tx_m	1	hs_sata_top_ctrlfpga_${index}_tx_m	0
add_con	in	ctrlfpga	hs_sata_top_${index}_rx_p	1	hs_sata_top_ctrlfpga_${index}_rx_p	0
add_con	in	ctrlfpga	hs_sata_top_${index}_rx_m	1	hs_sata_top_ctrlfpga_${index}_rx_m	0

!! 	}

!! for {set index 0} {$index < 10} {incr index 1} {
add_con	out	ctrlfpga	hs_sata_bottom_${index}_tx_p	1	hs_sata_bottom_ctrlfpga_${index}_tx_p	0
add_con	out	ctrlfpga	hs_sata_bottom_${index}_tx_m	1	hs_sata_bottom_ctrlfpga_${index}_tx_m	0
add_con	in	ctrlfpga	hs_sata_bottom_${index}_rx_p	1	hs_sata_bottom_ctrlfpga_${index}_rx_p	0
add_con	in	ctrlfpga	hs_sata_bottom_${index}_rx_m	1	hs_sata_bottom_ctrlfpga_${index}_rx_m	0

!! 	}

# DDR2 modules
!! for {set i 1} {$i <= 4} {incr i 1} {

# Data signals
add_con	bidir	ctrlfpga	membk${i}_dqs	9	ddr2ctrlfpga_${i}_dqs	0:8
add_con	bidir	ctrlfpga	membk${i}_dm	9	ddr2ctrlfpga_${i}_dm	0:8
add_con	bidir	ctrlfpga	membk${i}_dq	64	ddr2ctrlfpga_${i}_dq	0:63
add_con	bidir	ctrlfpga	membk${i}_cb	8	ddr2ctrlfpga_${i}_cb	0:7

# Address and commands signals
add_con	out	ctrlfpga	membk${i}_ba	2	ddr2ctrlfpga_${i}_ba	0:1
add_con	out	ctrlfpga	membk${i}_a		14	ddr2ctrlfpga_${i}_a	0:13
add_con	out	ctrlfpga	membk${i}_ras_	1	ddr2ctrlfpga_${i}_ras_	0
add_con	out	ctrlfpga	membk${i}_cas_	1	ddr2ctrlfpga_${i}_cas_	0
add_con	out	ctrlfpga	membk${i}_we_	1	ddr2ctrlfpga_${i}_we_	0

# Control signals
add_con	out	ctrlfpga	membk${i}_s_	2	ddr2ctrlfpga_${i}_s_	0:1
add_con	out	ctrlfpga	membk${i}_cke	1	ddr2ctrlfpga_${i}_cke	0
add_con	out	ctrlfpga	membk${i}_odt	2	ddr2ctrlfpga_${i}_odt	0:1

# Dqs div feedback loop
add_con	out	ctrlfpga	membk${i}_div_out	1	ddr2ctrlfpga_${i}_div_loop	0
add_con	in	ctrlfpga	membk${i}_div_in	1	ddr2ctrlfpga_${i}_div_loop	0

# Reset
add_con	out	ctrlfpga	membk${i}_reset_	1	ddr2ctrlfpga_${i}_reset_	0

# Clock signals
add_con	out	ctrlfpga	membk${i}_ck_p	3	ddr2ctrlfpga_${i}_ck_p	0:2
add_con	out	ctrlfpga	membk${i}_ck_m	3	ddr2ctrlfpga_${i}_ck_m	0:2

!! }

# Serial detect
add_con	out	ctrlfpga	mem_sda	1	ddr2ctrlfpga_sda	0
add_con	out	ctrlfpga	mem_scl	1	ddr2ctrlfpga_scl	0

# GPLEDs
add_net	ctrlfpga_gpleds 	${nb_gpleds_ctrl}
add_con 	out	ctrlfpga	gpleds	${nb_gpleds_ctrl}	ctrlfpga_gpleds	0:[expr $nb_gpleds_ctrl-1]

!! for {set index 1} {$index <= $nb_gpleds_ctrl} {incr index 1} {
add_blk	ctrlfpga_gpled_${index}	LED	a	c
def_param_blk	ctrlfpga_gpled_${index}	package	0603	part_number	BR1111C-TR	manufacturer	Stanley	www	http://rocky.digikey.com/WebLib/Stanley/AA1111C.pdf	description	LED RED 0603 SMD	distributor	Digikey	order_number	404-1000-1-ND	availability	available

add_con 	analog	ctrlfpga_gpled_${index}	a	1	ctrlfpga_gpleds	[expr $index-1]
add_con 	analog	ctrlfpga_gpled_${index}	c	1	GND			0
add_term	serial	ctrlfpga_gpled_${index}	c	[res_type 100R 1%]	1	[res 100R 1%]
!! }

# hswap enable
add_con	in	ctrlfpga	hswap_en	1	GND	0

# vbatt
add_con	pwr	ctrlfpga	vbatt		1	rtc_vbatt	0
add_term	serial	ctrlfpga	vbatt		[res_type 0R]	1	[res 0R]

# Main Power
add_con	pwr	ctrlfpga	vccint	76	VCC1_5	0	
!! add_bypass_hspeed_15 ctrlfpga_vccint 42 47nF
!! add_bypass_hspeed_15 ctrlfpga_vccint 21 470nF
!! add_bypass_bulk_15 ctrlfpga_vccint 11 4uF7
!! add_bypass_bulk_15 ctrlfpga_vccint 4 47uF

add_con	pwr	ctrlfpga	vccaux	32	VCC2_5	0	
!! add_bypass_hspeed_25 ctrlfpga_vccaux 18 47nF
!! add_bypass_hspeed_25 ctrlfpga_vccaux 9 470nF
!! add_bypass_bulk_25 ctrlfpga_vccaux 5 4uF7
!! add_bypass_bulk_25 ctrlfpga_vccaux 2 47uF

add_con	gnd	ctrlfpga	powergnd	216	GND		0	

# Banks Power
add_con	pwr	ctrlfpga	vcco_bk0_b	15	VCC2_5	0	
add_con	pwr	ctrlfpga	vcco_bk1_b	15	VCC2_5	0	
add_con	pwr	ctrlfpga	vcco_bk2_b	21	VCC1_8	0	
add_con	pwr	ctrlfpga	vcco_bk3_b	21	VCC1_8	0	
add_con	pwr	ctrlfpga	vcco_bk4_b	15	VCC2_5	0	
add_con	pwr	ctrlfpga	vcco_bk5_b	15	VCC2_5	0	
add_con	pwr	ctrlfpga	vcco_bk6_b	21	VCC1_8	0	
add_con	pwr	ctrlfpga	vcco_bk7_b	21	VCC1_8	0	

!! add_bypass_hspeed_18 ctrlfpga_vcco 47 47nF
!! add_bypass_hspeed_18 ctrlfpga_vcco 23 470nF
!! add_bypass_bulk_18 ctrlfpga_vcco 12 4uF7
!! add_bypass_bulk_18 ctrlfpga_vcco 5 47uF

!! add_bypass_hspeed_25 ctrlfpga_vcco 33 47nF
!! add_bypass_hspeed_25 ctrlfpga_vcco 17 470nF
!! add_bypass_bulk_25 ctrlfpga_vcco 9 4uF7
!! add_bypass_bulk_25 ctrlfpga_vcco 3 47uF

# DCI resistors
!! foreach i [list 2 3 6 7] {
add_net	ctrlfpga_vrn_bk${i}	1
add_net	ctrlfpga_vrp_bk${i}	1
add_con	analog	ctrlfpga	vrn_bk${i}	1	ctrlfpga_vrn_bk${i}	0
add_con	analog	ctrlfpga	vrp_bk${i}	1	ctrlfpga_vrp_bk${i}	0
add_term	drop	ctrlfpga	vrn_bk${i}	VCC1_8	[res_type 49R9 1%]	1	[res 49R9 1%]
add_term	drop	ctrlfpga	vrp_bk${i}	GND		[res_type 49R9 1%]	1	[res 49R9 1%]
!! }
!! foreach i [list 0 1 4 5] {
add_net	ctrlfpga_vrn_bk${i}	1
add_net	ctrlfpga_vrp_bk${i}	1
add_con	analog	ctrlfpga	vrn_bk${i}	1	ctrlfpga_vrn_bk${i}	0
add_con	analog	ctrlfpga	vrp_bk${i}	1	ctrlfpga_vrp_bk${i}	0
add_term	drop	ctrlfpga	vrn_bk${i}	VCC2_5	[res_type 49R9 1%]	1	[res 49R9 1%]
add_term	drop	ctrlfpga	vrp_bk${i}	GND		[res_type 49R9 1%]	1	[res 49R9 1%]
!! }

# Banks Vref
!! foreach i [list 2 3 6 7] {
add_con	analog	ctrlfpga	bk${i}_vref	13	ddr2_ctrlfpga_vref	0
add_term	net	ddr2_ctrlfpga_vref	GND	bypass_cap_ddr2_ctrlfpga_vref_bk${i}	[cap_type 100nF ceramic]	7	1	[cap 100nF ceramic]
!! }

 #       #    #   ####   #    #   ####    ####           #       #    #  #    #
 #       #    #  #    #  ##  ##  #    #  #               #       ##   #  #   #
 #       #    #  #       # ## #  #    #   ####           #       # #  #  ####
 #       #    #  #       #    #  #    #       #          #       #  # #  #  #
 #        #  #   #    #  #    #  #    #  #    #          #       #   ##  #   #
 ######    ##     ####   #    #   ####    ####           ######  #    #  #    #

# net creation
!! for {set index 1} {$index <= 4} {incr index 1} {
!!	set next [expr $index%4 + 1]
add_net	lvcmos_fpga${index}_2_fpga${next}		${horiz_lnk_size}
add_net	lvcmos_fpga${index}_2_ctrlfpga		${vert_lnk_size}
!! }

add_net	lvcmos_bus_d	${bus_data_lnk_size}
# data bus termination
!! for {set index 0} {$index < $bus_data_lnk_size} {incr index 1} {
!! 	set component [expr $index / 8]
!! 	set position [expr $index % 8]
!! 	if {[expr $index % 8] == 0} {

add_blk	lvcmos_bus_d_term_${component}_0	EXBE10C	r1	r2	r3	r4	r5	r6	r7	r8	com
def_param_blk	lvcmos_bus_d_term_${component}_0	package	custom	part_number	EXB-E10C470J	manufacturer	Panasonic	www	http://rocky.digikey.com/WebLib/Panasonic/Web%20data/EXB-A,E,D.pdf	description	8 resistors network	distributor	Digikey	order_number	U8470CT-ND	availability	available
add_con	in	lvcmos_bus_d_term_${component}_0	com	2	GND		0

add_blk	lvcmos_bus_d_term_${component}_1	EXBE10C	r1	r2	r3	r4	r5	r6	r7	r8	com
def_param_blk	lvcmos_bus_d_term_${component}_1	package	custom	part_number	EXB-E10C470J	manufacturer	Panasonic	www	http://rocky.digikey.com/WebLib/Panasonic/Web%20data/EXB-A,E,D.pdf	description	8 resistors network	distributor	Digikey	order_number	U8470CT-ND	availability	available
add_con	in	lvcmos_bus_d_term_${component}_1	com	2	GND		0

!! 	}
add_con	in	lvcmos_bus_d_term_${component}_0	r[expr $position+1]	1	lvcmos_bus_d	${index}
add_con	in	lvcmos_bus_d_term_${component}_1	r[expr $position+1]	1	lvcmos_bus_d	${index}
!! }
!! for {set i $index} {$i < [expr ($component+1) * 8]} {incr i 1} {
!! 	set position [expr $i % 8]
add_con_nc	lvcmos_bus_d_term_${component}_0	r[expr $position+1]	1
add_con_nc	lvcmos_bus_d_term_${component}_1	r[expr $position+1]	1
!! }

add_net	lvcmos_bus_c	${bus_ctrl_lnk_size}
# control bus termination
!! for {set index 0} {$index < $bus_ctrl_lnk_size} {incr index 1} {
!! 	set component [expr $index / 8]
!! 	set position [expr $index % 8]
!! 	if {[expr $index % 8] == 0} {

add_blk	lvcmos_bus_c_term_${component}_0	EXBE10C	r1	r2	r3	r4	r5	r6	r7	r8	com
def_param_blk	lvcmos_bus_c_term_${component}_0	package	custom	part_number	EXB-E10C470J	manufacturer	Panasonic	www	http://rocky.digikey.com/WebLib/Panasonic/Web%20data/EXB-A,E,D.pdf	description	8 resistors network	distributor	Digikey	order_number	U8470CT-ND	availability	available
add_con	in	lvcmos_bus_c_term_${component}_0	com	2	VCC1_8	0

add_blk	lvcmos_bus_c_term_${component}_1	EXBE10C	r1	r2	r3	r4	r5	r6	r7	r8	com
def_param_blk	lvcmos_bus_c_term_${component}_1	package	custom	part_number	EXB-E10C470J	manufacturer	Panasonic	www	http://rocky.digikey.com/WebLib/Panasonic/Web%20data/EXB-A,E,D.pdf	description	8 resistors network	distributor	Digikey	order_number	U8470CT-ND	availability	available
add_con	in	lvcmos_bus_c_term_${component}_1	com	2	VCC1_8	0

!! 	}
add_con	in	lvcmos_bus_c_term_${component}_0	r[expr $position+1]	1	lvcmos_bus_c	${index}
add_con	in	lvcmos_bus_c_term_${component}_1	r[expr $position+1]	1	lvcmos_bus_c	${index}
!! }
!! for {set i $index} {$i < [expr ($component+1) * 8]} {incr i 1} {
!! 	set position [expr $i % 8]
add_con_nc	lvcmos_bus_c_term_${component}_0	r[expr $position+1]	1

add_con_nc	lvcmos_bus_c_term_${component}_1	r[expr $position+1]	1
!! }

# vertical link
!! for {set index 1} {$index <= 4} {incr index 1} {
add_con	bidir	ctrlfpga	lvcmos_down_fpga${index}_d	${vert_lnk_size}	lvcmos_fpga${index}_2_ctrlfpga		0:[expr ${vert_lnk_size}-1]
!! }