# BEE2 board specification																																	

# DDR2 components																																

# Last Changes:																																	
# Pierre-Yves Droz	5/20/2004 1:48PM																																

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# DDR termination regulator
!! foreach fpga $fpgas {

add_blk	ddr2_reg_${fpga}	ML6554	vfb	shdn_	agnd	vrefout	vccq	avcc	dgnd	pgnd	vl	pvdd	vdd
def_param_blk	ddr2_reg_${fpga}	package	16PSOP	part_number	ML6554CU	manufacturer	Fairchild semiconductors	www	http://www.fairchildsemi.com/ds/ML/ML6554.pdf	description	Termination voltage regulator	distributor	Arrow	order_number	N/A	availability	available

# VCCQ
add_con	pwr	ddr2_reg_${fpga}	vccq	1	VCC1_8	0
add_term	drop	ddr2_reg_${fpga}	vccq	GND	[cap_type 100nF ceramic]	1	[cap 100nF ceramic]

# VDD - AVCC - PVDD
add_con	pwr	ddr2_reg_${fpga}	vdd	2	VCC2_5	0
add_con	pwr	ddr2_reg_${fpga}	avcc	1	VCC2_5	0
add_con	pwr	ddr2_reg_${fpga}	pvdd	2	VCC2_5	0
add_term	net	VCC2_5	GND	bypass_cap_25_ddr2_reg_${fpga}_vdd_220uF	[cap_type 220uF tantalum]	1	1	[cap 220uF tantalum]
add_term	net	VCC2_5	GND	bypass_cap_25_ddr2_reg_${fpga}_avcc_220uF	[cap_type 220uF tantalum]	1	1	[cap 220uF tantalum]
add_term	net	VCC2_5	GND	bypass_cap_25_ddr2_reg_${fpga}_pvdd_10uF	[cap_type 10uF ceramic_high_value]	1	1	[cap 10uF ceramic_high_value]

# SHDN_
add_net	ddr2reg${fpga}_shdn_	1
add_con	in	ddr2_reg_${fpga}	shdn_	1	ddr2reg${fpga}_shdn_	0
add_term	drop	ddr2_reg_${fpga}	shdn_	VCC2_5	[res_type 100K 1%]	1	[res 100K 1%]

# VREFOUT
add_net	ddr2_${fpga}_vref	1
add_con	out	ddr2_reg_${fpga}	vrefout	1	ddr2_${fpga}_vref	0
add_term	drop	ddr2_reg_${fpga}	vrefout	GND	[cap_type 100nF ceramic]	1	[cap 100nF ceramic]

# DGND - AGND - PGND
add_con	gnd	ddr2_reg_${fpga}	dgnd	2	GND	0
add_con	gnd	ddr2_reg_${fpga}	agnd	1	GND	0
add_con	gnd	ddr2_reg_${fpga}	pgnd	2	GND	0

# VL
add_net	ddr2_vtt_${fpga}	1
add_net	ddr2reg${fpga}_vl	1
add_con	pwr	ddr2_reg_${fpga}	vl	2	ddr2reg${fpga}_vl	0

add_term	net	ddr2_vtt_${fpga}	GND	ddr2reg${fpga}_output_bypass_cap_0	[cap_type 100nF ceramic] 	1	1	[cap 100nF ceramic]
add_term	net	ddr2_vtt_${fpga}	GND	ddr2reg${fpga}_output_bypass_cap_1	[cap_type 220uF tantalum]	1	1	[cap 220uF tantalum]
add_term	net	ddr2_vtt_${fpga}	GND	ddr2reg${fpga}_output_bypass_cap_2	[cap_type 220uF tantalum]	1	1	[cap 220uF tantalum]
add_term	net	ddr2_vtt_${fpga}	GND	ddr2reg${fpga}_output_bypass_cap_3	[cap_type 220uF tantalum]	1	1	[cap 220uF tantalum]

add_term	net	ddr2_vtt_${fpga}	ddr2reg${fpga}_vl	ddr2reg${fpga}_output_filter_ind	[ind_type 3uH5 7.5A]	1	1	[ind 3uH5 7.5A]

# VFB
add_net	ddr2reg${fpga}_vfb	1
add_net	ddr2reg${fpga}_vfb_tmp	1
add_con	in	ddr2_reg_${fpga}	vfb	1	ddr2reg${fpga}_vfb	0

add_term	net	ddr2_vtt_${fpga}		ddr2reg${fpga}_vfb	ddr2reg${fpga}_feedback_filter_0	[res_type 100K 1%]	1	1	[res 100K 1%]
add_term	net	ddr2_vtt_${fpga}		ddr2reg${fpga}_vfb_tmp	ddr2reg${fpga}_feedback_filter_1	[res_type 1K 1%]	1	1	[res 1K 1%]
add_term	net	ddr2reg${fpga}_vfb_tmp	ddr2reg${fpga}_vfb	ddr2reg${fpga}_feedback_filter_2	[cap_type 1nF ceramic]	1	1	[cap 1nF ceramic]

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!! 	for {set i 1} {$i <= 4} {incr i 1} {

# DDR2 dimm 240 socket
add_blk	ddr2_${fpga}_${i}	MOLEX87705	odt	ck_p	ck_m	cke	s_	ras_	cas_	we_	ba	ba2_gnd	a	dq	dqs	dm	cb	scl	sa0	sa1	sa2	sda	vdd	vddq	vref	vss	vddspd	reset_
def_param_blk	ddr2_${fpga}_${i}	package	custom	part_number	 877051001	manufacturer	Molex	www	http://www.molex.com/	description	DDR2 dimm-240 socket	distributor	Arrow	order_number	N/A	availability	available

# Data signals
add_net	ddr2${fpga}_${i}_dqs	9
add_net	ddr2${fpga}_${i}_dm	9
add_net	ddr2${fpga}_${i}_dq	64
add_net	ddr2${fpga}_${i}_cb	8
add_con	bidir	ddr2_${fpga}_${i}	dqs	9	ddr2${fpga}_${i}_dqs	0:8
add_con	bidir	ddr2_${fpga}_${i}	dm	9	ddr2${fpga}_${i}_dm	0:8
add_con	bidir	ddr2_${fpga}_${i}	dq	64	ddr2${fpga}_${i}_dq	0:63
add_con	bidir	ddr2_${fpga}_${i}	cb	8	ddr2${fpga}_${i}_cb	0:7

# Address and commands signals
add_net	ddr2${fpga}_${i}_ba	2
add_net	ddr2${fpga}_${i}_a	14
add_net	ddr2${fpga}_${i}_ras_	1
add_net	ddr2${fpga}_${i}_cas_	1
add_net	ddr2${fpga}_${i}_we_	1
add_con	in	ddr2_${fpga}_${i}	ba	2	ddr2${fpga}_${i}_ba	0:1
add_con	in	ddr2_${fpga}_${i}	a	14	ddr2${fpga}_${i}_a	0:13
add_con	in	ddr2_${fpga}_${i}	ras_	1	ddr2${fpga}_${i}_ras_	0
add_con	in	ddr2_${fpga}_${i}	cas_	1	ddr2${fpga}_${i}_cas_	0
add_con	in	ddr2_${fpga}_${i}	we_	1	ddr2${fpga}_${i}_we_	0

add_con	in	ddr2_${fpga}_${i}	ba2_gnd	1	GND			0

# Control signals
add_net	ddr2${fpga}_${i}_s_	2
add_net	ddr2${fpga}_${i}_cke	1
add_net	ddr2${fpga}_${i}_odt	2
add_con	in	ddr2_${fpga}_${i}	s_	2	ddr2${fpga}_${i}_s_	0:1
add_con	in	ddr2_${fpga}_${i}	cke	2	ddr2${fpga}_${i}_cke	0
add_con	in	ddr2_${fpga}_${i}	odt	2	ddr2${fpga}_${i}_odt	0:1

# Termination
!! foreach term {A B C D} {
add_blk	ddr2_term_${fpga}_${i}_${term}	EXBE10C	r1	r2	r3	r4	r5	r6	r7	r8	com
def_param_blk	ddr2_term_${fpga}_${i}_${term}	package	custom	part_number	EXB-E10C470J	manufacturer	Panasonic	www	http://rocky.digikey.com/WebLib/Panasonic/Web%20data/EXB-A,E,D.pdf	description	8 resistors network	distributor	Digikey	order_number	U8470CT-ND	availability	available
add_con	pwr	ddr2_term_${fpga}_${i}_${term}	com	2	ddr2_vtt_${fpga}		0
!! }

add_con_nc			ddr2_term_${fpga}_${i}_A	r1	1
add_con	analog	ddr2_term_${fpga}_${i}_A	r2	1	ddr2${fpga}_${i}_cke	0
add_con_nc			ddr2_term_${fpga}_${i}_A	r3	1
add_con	analog	ddr2_term_${fpga}_${i}_A	r4	1	ddr2${fpga}_${i}_a	12
add_con	analog	ddr2_term_${fpga}_${i}_A	r5	1	ddr2${fpga}_${i}_a	11
add_con	analog	ddr2_term_${fpga}_${i}_A	r6	1	ddr2${fpga}_${i}_a	9
add_con	analog	ddr2_term_${fpga}_${i}_A	r7	1	ddr2${fpga}_${i}_a	7
add_con	analog	ddr2_term_${fpga}_${i}_A	r8	1	ddr2${fpga}_${i}_a	8
add_con	analog	ddr2_term_${fpga}_${i}_B	r1	1	ddr2${fpga}_${i}_a	5
add_con	analog	ddr2_term_${fpga}_${i}_B	r2	1	ddr2${fpga}_${i}_a	6
add_con	analog	ddr2_term_${fpga}_${i}_B	r3	1	ddr2${fpga}_${i}_a	4
add_con	analog	ddr2_term_${fpga}_${i}_B	r4	1	ddr2${fpga}_${i}_a	3
add_con	analog	ddr2_term_${fpga}_${i}_B	r5	1	ddr2${fpga}_${i}_a	2
add_con	analog	ddr2_term_${fpga}_${i}_B	r6	1	ddr2${fpga}_${i}_a	1
add_con_nc			ddr2_term_${fpga}_${i}_B	r7	1
add_con_nc			ddr2_term_${fpga}_${i}_B	r8	1
add_con	analog	ddr2_term_${fpga}_${i}_C	r1	1	ddr2${fpga}_${i}_a	0
add_con_nc			ddr2_term_${fpga}_${i}_C	r2	1
add_con	analog	ddr2_term_${fpga}_${i}_C	r3	1	ddr2${fpga}_${i}_a	10
add_con	analog	ddr2_term_${fpga}_${i}_C	r4	1	ddr2${fpga}_${i}_ba	1
add_con	analog	ddr2_term_${fpga}_${i}_C	r5	1	ddr2${fpga}_${i}_ba	0
add_con_nc			ddr2_term_${fpga}_${i}_C	r6	1
add_con	analog	ddr2_term_${fpga}_${i}_C	r7	1	ddr2${fpga}_${i}_ras_	0
add_con	analog	ddr2_term_${fpga}_${i}_C	r8	1	ddr2${fpga}_${i}_we_	0
add_con	analog	ddr2_term_${fpga}_${i}_D	r1	1	ddr2${fpga}_${i}_s_	0
add_con	analog	ddr2_term_${fpga}_${i}_D	r2	1	ddr2${fpga}_${i}_cas_	0
add_con_nc			ddr2_term_${fpga}_${i}_D	r3	1
add_con_nc			ddr2_term_${fpga}_${i}_D	r4	1
add_con	analog	ddr2_term_${fpga}_${i}_D	r5	1	ddr2${fpga}_${i}_odt	0
add_con	analog	ddr2_term_${fpga}_${i}_D	r6	1	ddr2${fpga}_${i}_s_	1
add_con	analog	ddr2_term_${fpga}_${i}_D	r7	1	ddr2${fpga}_${i}_a	13
add_con	analog	ddr2_term_${fpga}_${i}_D	r8	1	ddr2${fpga}_${i}_odt	1

# dqs div feedback loop
add_net	ddr2${fpga}_${i}_div_loop	1

# Reset
add_net	ddr2${fpga}_${i}_reset_	1
add_con	in	ddr2_${fpga}_${i}	reset_	1	ddr2${fpga}_${i}_reset_	0
add_term	drop	ddr2_${fpga}_${i}	reset_	VCC1_8	[res_type 4K7]	1	[res 4K7]
add_term	drop	ddr2_${fpga}_${i}	reset_	GND		[res_type 4K7]	1	[res 4K7]	populate	for debug

# Clock signals
add_diff_net	ddr2${fpga}_${i}_ck	3
add_con	in	ddr2_${fpga}_${i}	ck_p	3	ddr2${fpga}_${i}_ck_p	0:2
add_con	in	ddr2_${fpga}_${i}	ck_m	3	ddr2${fpga}_${i}_ck_m	0:2

# vref
add_con	in	ddr2_${fpga}_${i}	vref	1	ddr2_${fpga}_vref		0
add_term	net	GND	ddr2_${fpga}_vref	bypass_cap_ddr2_${fpga}_${i}_vref_hspeed_0	[cap_type 100nF ceramic]	1	1	[cap 100nF ceramic]
add_term	net	GND	ddr2_${fpga}_vref	bypass_cap_ddr2_${fpga}_${i}_vref_hspeed_1	[cap_type 10nF ceramic] 	1	1	[cap 10nF ceramic]

# Power
add_con	pwr	ddr2_${fpga}_${i}	vdd		11	VCC1_8	0
add_con	pwr	ddr2_${fpga}_${i}	vddq		11	VCC1_8	0
add_con	pwr	ddr2_${fpga}_${i}	vddspd	1	VCC1_8	0
add_con	gnd	ddr2_${fpga}_${i}	vss		64	GND		0
!! add_bypass_bulk_18	ddr2_${fpga}_${i}_vdd 1
!! add_bypass_bulk_18	ddr2_${fpga}_${i}_vddq 1
!! add_bypass_hspeed_18	ddr2_${fpga}_${i}_vdd 11 100nF
!! add_bypass_hspeed_18	ddr2_${fpga}_${i}_vddq 11 100nF

!! 	}

# Serial detect
add_net	ddr2${fpga}_sda	1
add_net	ddr2${fpga}_scl	1
!! add_pullup_18	ddr2${fpga}_sda
!! add_pullup_18	ddr2${fpga}_scl

!! 	set saddrs [list "GND GND VCC1_8" "GND VCC1_8 GND" "GND VCC1_8 VCC1_8" "VCC1_8 GND GND"]
!! 	for {set i 1} {$i <= 4} {incr i 1} {
!! 	set saddr [lindex $saddrs [expr ($i-1)]]

add_con	in	ddr2_${fpga}_${i}	sda	1	ddr2${fpga}_sda		0
add_con	in	ddr2_${fpga}_${i}	scl	1	ddr2${fpga}_scl		0

add_con	in	ddr2_${fpga}_${i}	sa2	1	[lindex $saddr 0]		0
add_con	in	ddr2_${fpga}_${i}	sa1	1	[lindex $saddr 1]		0
add_con	in	ddr2_${fpga}_${i}	sa0	1	[lindex $saddr 2]		0

!!	}

!! }