# BEE2 board specification

# Xilinx XC2VP70 user FPGA

# Last Changes:
# Pierre-Yves Droz	5/20/2004 1:50PM

# Best viewed with tab_length=6


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# Infiniband ports
!! set infiniband_links ""
!! for {set i 0} {$i < 4} {incr i 1} {
!! 	set infiniband_links "${infiniband_links}	infiniband_${i}_tx_p	infiniband_${i}_tx_m	infiniband_${i}_rx_p	infiniband_${i}_rx_m"
!! }

# High speed Serial ATA ports
!! set hs_sata_port ""
!! for {set i 0} {$i < 2} {incr i 1} {
!! 	set hs_sata_port "${hs_sata_port}	hs_sata_top_${i}_tx_p	hs_sata_top_${i}_tx_m	hs_sata_top_${i}_rx_p	hs_sata_top_${i}_rx_m"
!! 	set hs_sata_port "${hs_sata_port}	hs_sata_bottom_${i}_tx_p	hs_sata_bottom_${i}_tx_m	hs_sata_bottom_${i}_rx_p	hs_sata_bottom_${i}_rx_m"
!! }

# FPGA VCCOs
!! set vccos ""
!! for {set i 0} {$i < 8} {incr i 1} {
!! 	set vccos "${vccos}	vcco_bk${i}_b"
!! }

# FPGA DCI resistors
!! set vrs ""
!! for {set i 0} {$i < 8} {incr i 1} {
!! 	set vrs "${vrs}	vrn_bk${i}	vrp_bk${i}"
!! }

# FPGA Vrefs
!! set vrefs ""
!! foreach i [list 2 3 6 7] {
!! 	set vrefs "${vrefs}	bk${i}_vref"
!! }

# Memory modules
!! set mems ""
!! for {set i 1} {$i <= 4} {incr i 1} {
!! 	set mems "${mems}		membk${i}_s_	membk${i}_odt	membk${i}_ck_p	membk${i}_ck_m	membk${i}_cke	membk${i}_div_out	membk${i}_div_in	membk${i}_ras_	membk${i}_cas_	membk${i}_we_	membk${i}_ba	membk${i}_a	membk${i}_dq	membk${i}_dqs	membk${i}_dm	membk${i}_cb	membk${i}_reset_"
!! }

!! foreach fpga $usr_fpgas {
# FPGA																																	
add_blk	${fpga}	XCV2P70_usr	sysclk_p	sysclk_m	usrclk_p	usrclk_m	tdi	tdo	tms	tck	prog_	init_	cfgmode0_b	cfgmode1_b	cfgmode2_b	done	dxp	dxn	cfg_cclk	cfg_data	cfg_cs_	cfg_rdwr_	avccauxtx_top	avccauxrx_top	vttx_top	vtrx_top	gnda_top	avccauxtx_bottom	avccauxrx_bottom	vttx_bottom	vtrx_bottom	gnda_bottom	brefclk_top_p	brefclk_top_m	brefclk2_top_p	brefclk2_top_m	brefclk_bottom_p	brefclk_bottom_m	brefclk2_bottom_p	brefclk2_bottom_m	${infiniband_links}	${hs_sata_port}	lvcmos_right	lvcmos_left	lvcmos_top	lvcmos_bus_c	lvcmos_bus_d	mem_scl	mem_sda	${mems}	gpio	gpleds	reset_	hswap_en	vbatt	vccint	vccaux	${vccos}	${vrefs}	${vrs}	powergnd
def_param_blk	${fpga}	package	1704BGA	part_number	2V2P70	manufacturer	Xilinx	www	http://direct.xilinx.com/bvdocs/publications/ds083.pdf	description	FPGA	distributor	Xilinx	order_number	N/A	availability	see with Xilinx

# System clock input
add_con	in	${fpga}	sysclk_p	1	sysclk_${fpga}_p	0
add_con	in	${fpga}	sysclk_m	1	sysclk_${fpga}_m	0

# User clock input
add_con	in	${fpga}	usrclk_p	1	usrclk_${fpga}_p	0
add_con	in	${fpga}	usrclk_m	1	usrclk_${fpga}_m	0

# Reset
add_net	${fpga}_reset_	1
add_con	in	${fpga}	reset_	1	${fpga}_reset_	0
add_term	drop	${fpga}	reset_	VCC1_8	[res_type 1K 1%]	1	[res 1K 1%]
add_term	drop	${fpga}	reset_	GND		[cap_type 10uF tantalum]	1	[cap 10uF tantalum]

add_term	drop	${fpga}	reset_	GND		HDR_2	1	[hdr SW_Reset_PB 1x2]
add_term	drop	${fpga}	reset_	GND		[sw_type SW_Reset]	1	[sw SW_Reset]

# Configuration selectmap bus
add_con	in	${fpga}	prog_	1	cfg_prog_${fpga}_		0
add_con	bidir	${fpga}	init_	1	cfg_init_${fpga}_		0
add_con	in	${fpga}	cfg_cs_	1	cfg_cs_${fpga}_	0
add_con	in	${fpga}	cfg_cclk	1	cfg_cclk_fpga	0	
add_con	in	${fpga}	cfg_data	8	cfg_data_${fpga}	0:7	
add_con	in	${fpga}	cfg_rdwr_	1	cfg_rdwr_${fpga}_	0	

# Configuration mode - M2M1M0 is 110 for slave selectmap
add_blk	${fpga}_cfgmode_hdr	HDR_2X3_CFGMODE	cfgmode0	cfgmode1	cfgmode2	cfgmode0_p	cfgmode1_p	cfgmode2_p
def_param_blk	${fpga}_cfgmode_hdr	[hdr USRFPGAS_MODE 2x3]

add_net	${fpga}_cfgmode0	1
add_con	in	${fpga}	cfgmode0_b	1	${fpga}_cfgmode0	0
!! add_pulldown ${fpga}_cfgmode0
add_con	out	${fpga}_cfgmode_hdr	cfgmode0	1	${fpga}_cfgmode0	0
add_con	in	${fpga}_cfgmode_hdr	cfgmode0_p	1	VCC2_5		0

add_net	${fpga}_cfgmode1	1
add_con	in	${fpga}	cfgmode1_b	1	${fpga}_cfgmode1	0
!! add_pulldown ${fpga}_cfgmode1
add_con	out	${fpga}_cfgmode_hdr	cfgmode1	1	${fpga}_cfgmode1	0
add_con	in	${fpga}_cfgmode_hdr	cfgmode1_p	1	VCC2_5		0

add_net	${fpga}_cfgmode2	1
add_con	in	${fpga}	cfgmode2_b	1	${fpga}_cfgmode2	0
!! add_pulldown ${fpga}_cfgmode2
add_con	out	${fpga}_cfgmode_hdr	cfgmode2	1	${fpga}_cfgmode2	0
add_con	in	${fpga}_cfgmode_hdr	cfgmode2_p	1	VCC2_5		0

# Done led
add_con	out	${fpga}	done	1	cfg_done_${fpga}	0
add_term	drop	${fpga}	done	VCC2_5	[res_type 511R 1%]	1	[res 511R 1%]

add_net	cfg_done_${fpga}_cat	1

add_blk	${fpga}_doneled	LED	a	c
def_param_blk	${fpga}_doneled	package	0603	part_number	PG1111C-TR	manufacturer	Panasonic	www	http://rocky.digikey.com/WebLib/Stanley/AA1111C.pdf	description	LED GREEN 0603 SMD	distributor	Digikey	order_number	404-1004-1-ND	availability	available

add_con	pwr	${fpga}_doneled	a	1	VCC3_3		0
add_con	pwr	${fpga}_doneled	c	1	cfg_done_${fpga}_cat	0

add_term	serial	${fpga}_doneled	a	[res_type 511R 1%]	1	[res 511R 1%]

add_blk	transistor_${fpga}_done	BSS138	g	d	s
def_param_blk	transistor_${fpga}_done	package	SOT23	part_number	BSS138TA	manufacturer	Zetex	www	http://www.zetex.com/3.0/pdf/BSS138.pdf	description	MOSFET N-CHAN 50V 200MA SOT-23	distributor	Digikey	order_number	BSS138ZXCT-ND	availability	available
add_con	analog	transistor_${fpga}_done	s	1	GND				0
add_con	analog	transistor_${fpga}_done	d	1	cfg_done_${fpga}_cat		0
add_con	analog	transistor_${fpga}_done	g	1	cfg_done_${fpga}		0

# Temperature sensor
add_con	analog	${fpga}	dxp	1	temp_${fpga}_dx_p	0
add_con	analog	${fpga}	dxn	1	temp_${fpga}_dx_m	0

# MGTs Power
!! 	foreach side [list top bottom] {
add_con	pwr	${fpga}	avccauxtx_${side}	10	avccauxtx_${fpga}_${side}	0:9
add_con	pwr	${fpga}	avccauxrx_${side}	10	avccauxrx_${fpga}_${side}	0:9
add_con	pwr	${fpga}	vttx_${side}	10	vttx_${fpga}_${side}	0:9
add_con	pwr	${fpga}	vtrx_${side}	10	vtrx_${fpga}_${side}	0:9

add_con	gnd	${fpga}	gnda_${side}	10	MGT_GND_${fpga}_${side}	0
!! 	}

# MGTs Clock
add_con	in	${fpga}	brefclk_top_p	1	mgt_${fpga}_top_clk1_p	0
add_con	in	${fpga}	brefclk_top_m	1	mgt_${fpga}_top_clk1_m	0
add_con	in	${fpga}	brefclk2_top_p	1	mgt_${fpga}_top_clk2_p	0
add_con	in	${fpga}	brefclk2_top_m	1	mgt_${fpga}_top_clk2_m	0
add_con	in	${fpga}	brefclk_bottom_p	1	mgt_${fpga}_bottom_clk1_p	0
add_con	in	${fpga}	brefclk_bottom_m	1	mgt_${fpga}_bottom_clk1_m	0
add_con	in	${fpga}	brefclk2_bottom_p	1	mgt_${fpga}_bottom_clk2_p	0
add_con	in	${fpga}	brefclk2_bottom_m	1	mgt_${fpga}_bottom_clk2_m	0

# MGTs Infiniband signals
!! for {set index 0} {$index < 4} {incr index 1} {
add_con	out	${fpga}	infiniband_${index}_tx_p	4	infiniband_${fpga}_${index}_tx_p	0:3
add_con	out	${fpga}	infiniband_${index}_tx_m	4	infiniband_${fpga}_${index}_tx_m	0:3
add_con	in	${fpga}	infiniband_${index}_rx_p	4	infiniband_${fpga}_${index}_rx_p	0:3
add_con	in	${fpga}	infiniband_${index}_rx_m	4	infiniband_${fpga}_${index}_rx_m	0:3

!! 	foreach dir [list rx tx] {
!! 		for {set i 0} {$i < $put_via(${fpga}_${dir}_${index})} {incr i 1} {
!! 			for {set j 0} {$j < 4} {incr j 1} {
add_blk	diff_via_${dir}_${fpga}_${index}_${j}_${i}	DIFF_VIA	p	m	signalgnd
def_param_blk	diff_via_${dir}_${fpga}_${index}_${j}_${i}	virtual_part	true

add_con	analog	diff_via_${dir}_${fpga}_${index}_${j}_${i}	p		1	infiniband_${fpga}_${index}_${dir}_p	$j
add_con	analog	diff_via_${dir}_${fpga}_${index}_${j}_${i}	m		1	infiniband_${fpga}_${index}_${dir}_m	$j
add_con	gnd		diff_via_${dir}_${fpga}_${index}_${j}_${i}	signalgnd	2	GND	0

!!			}
!!		}
!! 	}

!! }

# MGTs High speed serial ATA signals
!! for {set index 0} {$index < 2} {incr index 1} {
add_con	out	${fpga}	hs_sata_top_${index}_tx_p	1	hs_sata_top_${fpga}_${index}_tx_p	0
add_con	out	${fpga}	hs_sata_top_${index}_tx_m	1	hs_sata_top_${fpga}_${index}_tx_m	0
add_con	in	${fpga}	hs_sata_top_${index}_rx_p	1	hs_sata_top_${fpga}_${index}_rx_p	0
add_con	in	${fpga}	hs_sata_top_${index}_rx_m	1	hs_sata_top_${fpga}_${index}_rx_m	0

add_con	out	${fpga}	hs_sata_bottom_${index}_tx_p	1	hs_sata_bottom_${fpga}_${index}_tx_p	0
add_con	out	${fpga}	hs_sata_bottom_${index}_tx_m	1	hs_sata_bottom_${fpga}_${index}_tx_m	0
add_con	in	${fpga}	hs_sata_bottom_${index}_rx_p	1	hs_sata_bottom_${fpga}_${index}_rx_p	0
add_con	in	${fpga}	hs_sata_bottom_${index}_rx_m	1	hs_sata_bottom_${fpga}_${index}_rx_m	0

!! 	}


# DDR2 modules
!! for {set i 1} {$i <= 4} {incr i 1} {

# Data signals
add_con	bidir	${fpga}	membk${i}_dqs	9	ddr2${fpga}_${i}_dqs	0:8
add_con	bidir	${fpga}	membk${i}_dm	9	ddr2${fpga}_${i}_dm	0:8
add_con	bidir	${fpga}	membk${i}_dq	64	ddr2${fpga}_${i}_dq	0:63
add_con	bidir	${fpga}	membk${i}_cb	8	ddr2${fpga}_${i}_cb	0:7

# Address and commands signals
add_con	out	${fpga}	membk${i}_ba	2	ddr2${fpga}_${i}_ba	0:1
add_con	out	${fpga}	membk${i}_a		14	ddr2${fpga}_${i}_a	0:13
add_con	out	${fpga}	membk${i}_ras_	1	ddr2${fpga}_${i}_ras_	0
add_con	out	${fpga}	membk${i}_cas_	1	ddr2${fpga}_${i}_cas_	0
add_con	out	${fpga}	membk${i}_we_	1	ddr2${fpga}_${i}_we_	0

# Control signals
add_con	out	${fpga}	membk${i}_s_	2	ddr2${fpga}_${i}_s_	0:1
add_con	out	${fpga}	membk${i}_cke	1	ddr2${fpga}_${i}_cke	0
add_con	out	${fpga}	membk${i}_odt	2	ddr2${fpga}_${i}_odt	0:1

# Dqs div feedback loop
add_con	out	${fpga}	membk${i}_div_out	1	ddr2${fpga}_${i}_div_loop	0
add_con	in	${fpga}	membk${i}_div_in	1	ddr2${fpga}_${i}_div_loop	0

# Reset
add_con	out	${fpga}	membk${i}_reset_	1	ddr2${fpga}_${i}_reset_	0

# Clock signals
add_con	out	${fpga}	membk${i}_ck_p	3	ddr2${fpga}_${i}_ck_p	0:2
add_con	out	${fpga}	membk${i}_ck_m	3	ddr2${fpga}_${i}_ck_m	0:2

!! }

# Serial detect
add_con	out	${fpga}	mem_sda	1	ddr2${fpga}_sda	0
add_con	out	${fpga}	mem_scl	1	ddr2${fpga}_scl	0

# GPIO
add_net	${fpga}_gpio	${nb_gpios}
add_con	bidir	${fpga}		gpio		${nb_gpios}			${fpga}_gpio	0:[expr $nb_gpios-1]

add_blk	gpio_${fpga}	HDR_2X11_GPIO	pins	vcc	powergnd
def_param_blk	gpio_${fpga}	[hdr GPIO_A 2x11]

add_con	pwr	gpio_${fpga}	vcc		1	VCC1_8	0
add_con	gnd	gpio_${fpga}	powergnd	1	GND		0

add_con	bidir	gpio_${fpga}	pins		${nb_gpios}	${fpga}_gpio	0:[expr $nb_gpios-1]

# GPLEDs
add_net	${fpga}_gpleds 	${nb_gpleds}
add_con 	out	${fpga}	gpleds	${nb_gpleds}	${fpga}_gpleds	0:[expr $nb_gpleds-1]

!! for {set index 1} {$index <= $nb_gpleds} {incr index 1} {
add_blk	${fpga}_gpled_${index}	LED	a	c
def_param_blk	${fpga}_gpled_${index}	package	0603	part_number	BR1111C-TR	manufacturer	Stanley	www	http://rocky.digikey.com/WebLib/Stanley/AA1111C.pdf	description	LED RED 0603 SMD	distributor	Digikey	order_number	404-1000-1-ND	availability	available

add_con 	analog	${fpga}_gpled_${index}	a	1	${fpga}_gpleds	[expr $index-1]
add_con 	analog	${fpga}_gpled_${index}	c	1	GND			0
add_term	serial	${fpga}_gpled_${index}	c	[res_type 100R 1%]	1	[res 100R 1%]
!! }

# hswap enable
add_con	in	${fpga}	hswap_en	1	GND	0

# vbatt
add_con	pwr	${fpga}	vbatt		1	rtc_vbatt	0
add_term	serial	${fpga}	vbatt		[res_type 0R]	1	[res 0R]

# Main Power
add_con	pwr	${fpga}	vccint	76	VCC1_5	0	
!! add_bypass_hspeed_15 ${fpga}_vccint 42 47nF
!! add_bypass_hspeed_15 ${fpga}_vccint 21 470nF
!! add_bypass_bulk_15 ${fpga}_vccint 11 4uF7
!! add_bypass_bulk_15 ${fpga}_vccint 4 47uF

add_con	pwr	${fpga}	vccaux	32	VCC2_5	0	
!! add_bypass_hspeed_25 ${fpga}_vccaux 18 47nF
!! add_bypass_hspeed_25 ${fpga}_vccaux 9 470nF
!! add_bypass_bulk_25 ${fpga}_vccaux 5 4uF7
!! add_bypass_bulk_25 ${fpga}_vccaux 2 47uF

add_con	gnd	${fpga}	powergnd	216	GND		0	

# Banks Power
add_con	pwr	${fpga}	vcco_bk0_b	15	VCC2_5	0	
add_con	pwr	${fpga}	vcco_bk1_b	15	VCC2_5	0	
add_con	pwr	${fpga}	vcco_bk2_b	21	VCC1_8	0	
add_con	pwr	${fpga}	vcco_bk3_b	21	VCC1_8	0	
add_con	pwr	${fpga}	vcco_bk4_b	15	VCC2_5	0	
add_con	pwr	${fpga}	vcco_bk5_b	15	VCC2_5	0	
add_con	pwr	${fpga}	vcco_bk6_b	21	VCC1_8	0	
add_con	pwr	${fpga}	vcco_bk7_b	21	VCC1_8	0	

!! add_bypass_hspeed_18 ${fpga}_vcco 47 47nF
!! add_bypass_hspeed_18 ${fpga}_vcco 23 470nF
!! add_bypass_bulk_18 ${fpga}_vcco 12 4uF7
!! add_bypass_bulk_18 ${fpga}_vcco 5 47uF

!! add_bypass_hspeed_25 ${fpga}_vcco 33 47nF
!! add_bypass_hspeed_25 ${fpga}_vcco 17 470nF
!! add_bypass_bulk_25 ${fpga}_vcco 9 4uF7
!! add_bypass_bulk_25 ${fpga}_vcco 3 47uF

# DCI resistors
!! foreach i [list 2 3 6 7] {
add_net	${fpga}_vrn_bk${i}	1
add_net	${fpga}_vrp_bk${i}	1
add_con	analog	${fpga}	vrn_bk${i}	1	${fpga}_vrn_bk${i}	0
add_con	analog	${fpga}	vrp_bk${i}	1	${fpga}_vrp_bk${i}	0
add_term	drop	${fpga}	vrn_bk${i}	VCC1_8	[res_type 49R9 1%]	1	[res 49R9 1%]
add_term	drop	${fpga}	vrp_bk${i}	GND		[res_type 49R9 1%]	1	[res 49R9 1%]
!! 	}
!! foreach i [list 0 1 4 5] {
add_net	${fpga}_vrn_bk${i}	1
add_net	${fpga}_vrp_bk${i}	1
add_con	analog	${fpga}	vrn_bk${i}	1	${fpga}_vrn_bk${i}	0
add_con	analog	${fpga}	vrp_bk${i}	1	${fpga}_vrp_bk${i}	0
add_term	drop	${fpga}	vrn_bk${i}	VCC2_5	[res_type 49R9 1%]	1	[res 49R9 1%]
add_term	drop	${fpga}	vrp_bk${i}	GND		[res_type 49R9 1%]	1	[res 49R9 1%]
!! 	}

# Banks Vref
!! 	foreach i [list 2 3 6 7] {
add_con	analog	${fpga}	bk${i}_vref	13	ddr2_${fpga}_vref		0
add_term	net	ddr2_${fpga}_vref	GND	bypass_cap_ddr2_${fpga}_vref_bk${i}	[cap_type 100nF ceramic]	7	1	[cap 100nF ceramic]
!! 	}

!! }

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# Code proper to FPGA1

# JTAG configuration port
add_con	in	fpga1	tdi	1	userfpgas_jtag_con_2_fpga1		0
add_con	out	fpga1	tdo	1	userfpgas_jtag_fpga1_2_fpga2		0
add_con	in	fpga1	tck	1	userfpgas_jtag_tck			0
add_con	in	fpga1	tms	1	userfpgas_jtag_tms			0

add_term	net	userfpgas_jtag_con_2_fpga1	userfpgas_jtag_fpga1_2_fpga2	jtag_bypass_fpga1_res	[res_type 0R]	1	1	[res 0R]	populate	when fpga1 is not populated

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# Code proper to FPGA2

# JTAG configuration port
add_con	in	fpga2	tdi	1	userfpgas_jtag_fpga1_2_fpga2		0
add_con	out	fpga2	tdo	1	userfpgas_jtag_fpga2_2_fpga3		0
add_con	in	fpga2	tck	1	userfpgas_jtag_tck			0
add_con	in	fpga2	tms	1	userfpgas_jtag_tms			0

add_term	net	userfpgas_jtag_fpga1_2_fpga2	userfpgas_jtag_fpga2_2_fpga3	jtag_bypass_fpga2_res	[res_type 0R]	1	1	[res 0R]	populate	when fpga2 is not populated


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# Code proper to FPGA3

# JTAG configuration port
add_con	in	fpga3	tdi	1	userfpgas_jtag_fpga2_2_fpga3		0
add_con	out	fpga3	tdo	1	userfpgas_jtag_fpga3_2_fpga4		0
add_con	in	fpga3	tck	1	userfpgas_jtag_tck			0
add_con	in	fpga3	tms	1	userfpgas_jtag_tms			0

add_term	net	userfpgas_jtag_fpga2_2_fpga3	userfpgas_jtag_fpga3_2_fpga4	jtag_bypass_fpga3_res	[res_type 0R]	1	1	[res 0R]	populate	when fpga3 is not populated


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# Code proper to FPGA4

# JTAG configuration port
add_con	in	fpga4	tdi	1	userfpgas_jtag_fpga3_2_fpga4		0
add_con	out	fpga4	tdo	1	userfpgas_jtag_fpga4_2_con		0
add_con	in	fpga4	tck	1	userfpgas_jtag_tck			0
add_con	in	fpga4	tms	1	userfpgas_jtag_tms			0

add_term	net	userfpgas_jtag_fpga3_2_fpga4	userfpgas_jtag_fpga4_2_con	jtag_bypass_fpga4_res	[res_type 0R]	1	1	[res 0R]	populate	when fpga4 is not populated	


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!! for {set index 1} {$index <= 4} {incr index 1} {
!!	set next [expr $index%4 + 1]
!!	set prev [expr ($index-2)%4 + 1]
add_con	bidir	fpga${index}	lvcmos_right	${horiz_lnk_size}	lvcmos_fpga${prev}_2_fpga${index}	0:[expr ${horiz_lnk_size}-1]

add_con	bidir	fpga${index}	lvcmos_left		${horiz_lnk_size}	lvcmos_fpga${index}_2_fpga${next}	0:[expr ${horiz_lnk_size}-1]

add_con	bidir	fpga${index}	lvcmos_top		${vert_lnk_size}	lvcmos_fpga${index}_2_ctrlfpga	0:[expr ${vert_lnk_size}-1]

add_con	bidir	fpga${index}	lvcmos_bus_d	${bus_data_lnk_size}	lvcmos_bus_d			0:[expr ${bus_data_lnk_size}-1]

add_con	bidir	fpga${index}	lvcmos_bus_c	${bus_ctrl_lnk_size}	lvcmos_bus_c			0:[expr ${bus_ctrl_lnk_size}-1]
!! }