Block Creators FAQ
Other useful FAQs:
The ADC board FAQ - AdcFaq
The MSSGE FAQ - MssgeFaq
The IBOB board FAQ - IbobFaq
The BEE2 board FAQ - Bee2Faq
Frequently Asked Questions
What are the steps for creating a new block ?
The first step for interfacing a BEE hardware component into the toolflow is to create a simulink block which matches the port listings of the VHDL you want to interface. Next, add a functional simulink model in a subsystem which is disregarded for generation.
Simulink object must have the tag property 'xps:<name>', which can be set by right-clicking the simulink block and editing 'Block Properties'. This property tells the toolflow which directory to examine for implementation details of your block, as described next.
In xps_library there are a bunch of directories prefixed with '@' that represent each BEE hardware component. By default, a new block inherits all the properties from the '@xps_block' directory. To add a component, you need to make a new directory here.
Next, copy any files from '@xps_block' into your directory that you want to implement differently.
What follows is for EDK stuff...
The base system is under hitz\designs\bee\lib\xps_lib.
For testing and development replace 'xps_lib' with 'xps_lib_devel'.
Unzip a base system.
Your IP must be in '\\hitz\designs\bee\lib\xps_lib\XPS_..._base\pcores'.
Here there are 3 dirs: data=mpd file (describes port, etc, of IP), hdl=source code, and netlist=netlist files(edn,ngc).
MHS file in root of base system. It is an EDK design which enumerates IPs, their interfaces to bus, parameters like addresses, and a map of what external nets get attached to which IP ports.
We need to write the code which will write the entries in the mhs and mpd files, vhdl wrappers around the simulink netlist (to create the appropriate bus interface), and then we need to write C code for communicating with the en.
display.m = Needs to be edited to display parameters. Outputs debug info only.
xps_<name>.m = The block constructor, makes a matlab object out of a simulink object. Besides normal name changes, add any parameters to the matlab object constructor which will be necessary to make all later decisions.
drc.m = makes any drc checks you need.
elaborate.m = Adds port types to the object. Needs to know the gateway names generated by the simulink block.
gen_cmds.m = Any C commands you need for talking to your block from the command line.
gen_mhs_external = Modify output ports of the chip.
gen_mhs_ip.m = Generates port instations for the new block you are adding. Here's where you interface the block to the bus, and where you define what VHDL or Verilog core you are interfacing to. Don't forget the clk line (available under xsg_obj's 'clk_src'), which was made implicitly by simulink. Each block has a range of addresses going from baseaddr to highaddr, and you be sure to include a line about attaching the IP block to the bus ('SOPB' = slave opb device).
gen_mhs_xsg.m = Generates port instantiations for the simulink IP which are what ties to the new block. These aren't the raw interfaces to the simulink design--they're from the mpd file.
gen_mpd_bus.m = For implementing bus interfaces between IP blocks. Necessary for BRAM-like interfaces.
gen_mpd_options.m = For giving special options to the simulink IP.
gen_mpd_port.m = Generates the port wrapper around the similink IP which we referred to in gen_mhs_xsg.m.
gen_mss.m = Tells EDK what special software libraries (drivers) this block uses.
gen_src_files.m = For special software.
gen_src_main.m = For special software.
gen_ucf.m = User constraints for any external lines.
gen_vhdl_*_def.m = Defines top level VHDL * definitions for wrapping the Simulink netlist.
get.m & set.m = For getting & setting fields in an object.
probe_bus_usage.m = Set the flag for which bus (plb or opb) to use.
wseval.m = used for accessing variables values.