• Bee2CoreOpbSelectMapV101a

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Created: 2006-06-05

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1. Introduction
2. Functional Description
3. Parameters
4. Instantiation
5. Register Definition
6. Interrupt Behavior
7. Drivers
8. Frequently Asked Questions
9. Core Facts
10. Revision History

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Introduction

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The OPB SelectMAP controller core provides the ability to independently program and communicate with the four BEE2 user FPGAs. The core connects to the OPB bus via the Xilinx IPIF interface and provides a simple, register based interface to the user. The core provides two modes of operation, programming mode and FIFO mode. In programming mode the core can independently set and readback the configuration bitstreams of each user FPGA and also controls each FPGA PROG pin. In FIFO mode, the core can be used in conjunction with the opb_selectmap_fifo core in the user FPGA to provide a low-speed communication channel.

Two device driver models are currently available which utilize the core. First, the BORPH/Linux operating system has integrated support for the core and uses it to both program the user FPGAs on demand and as a control channel. Second, a generic Linux character device driver is available that allows easy programming and file I/O style communication with the user FPGA logic.

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Functional Description

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The primary use of this core is to transfer bytes of data over the SelectMAP bus (more information about the SelectMAP bus can be found in the Virtex-II Pro User Guide). The SelectMAP bus can operate in two modes. When unconfigured the SelectMAP pins on the FPGA are used to program and readback configuration information. After configuration the pins can either continue to operate as configuration pins or can become general purpose I/O. The OPB SelectMAP controller core provides two modes of operation that allow both configuration and reuse of the SelectMAP pins after configuration as a general purpose 8-bit data bus.

In both modes the core does not provide any hardware buffering. In configuration mode the transfer timing is completely deterministic (actually there are modes that are non-deterministic, such as configuring an encrypted bitstream, however these require the use of the BUSY signal which is not connected to the control FPGA of the BEE2) and in data transfer mode all buffering is done at the user FPGA. The buffering is performed at the user FPGA to accomodate the limited number of control signals available after configuration. To operating in data transfer mode (also known as FIFO mode), the user FPGA bitstream must contain the corresponding opb_selectmap_fifo core.

The core provides four independent SelectMAP interfaces, each connected to one user FPGA. Each interface is controlled by a pair of registers, the control and data registers. The control register contains information about the configuration state of the chip (i.e. the state of the PROG_B pin) as well as interrupt state and the core mode (i.e. configuration or FIFO mode). The primary interaction with the core is through the data register. The data register provides single byte transfers of data to or from the user FPGA. In configuration mode the writes result in normal SelectMAP configuration writes, while reads result in readback of configuration data if the proper read command has already been issued via writes. In FIFO mode reads and writes transfer a single byte at a time from or to the FIFO on the user FPGA. Currently the FIFO depth is fixed at 129 bytes.

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Parameters

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This core takes no parameters outside the standard IPIF parameters.

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Instantiation

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Instantiation of the core in a Platform Studio design is similar to any other core that attaches to a bus and has external ports. The following external ports need to be attached to external nets in the MHS file and constraints need to be added to the system UCF file from the file found in the core's ucf directory.

 PORT FPGA_CCLK    = FPGA_CCLK,    DIR = O
 PORT FPGA1_D      = FPGA1_D,      DIR = IO, VEC = [0:7]
 PORT FPGA1_RDWR_B = FPGA1_RDWR_B, DIR = O
 PORT FPGA1_CS_B   = FPGA1_CS_B,   DIR = O
 PORT FPGA1_INIT_B = FPGA1_INIT_B, DIR = I
 PORT FPGA1_DONE   = FPGA1_DONE,   DIR = I
 PORT FPGA1_PROG_B = FPGA1_PROG_B, DIR = O
 PORT FPGA2_D      = FPGA2_D,      DIR = IO, VEC = [0:7]
 PORT FPGA2_RDWR_B = FPGA2_RDWR_B, DIR = O
 PORT FPGA2_CS_B   = FPGA2_CS_B,   DIR = O
 PORT FPGA2_INIT_B = FPGA2_INIT_B, DIR = I
 PORT FPGA2_DONE   = FPGA2_DONE,   DIR = I
 PORT FPGA2_PROG_B = FPGA2_PROG_B, DIR = O
 PORT FPGA3_D      = FPGA3_D,      DIR = IO, VEC = [0:7]
 PORT FPGA3_RDWR_B = FPGA3_RDWR_B, DIR = O
 PORT FPGA3_CS_B   = FPGA3_CS_B,   DIR = O
 PORT FPGA3_INIT_B = FPGA3_INIT_B, DIR = I
 PORT FPGA3_DONE   = FPGA3_DONE,   DIR = I
 PORT FPGA3_PROG_B = FPGA3_PROG_B, DIR = O
 PORT FPGA4_D      = FPGA4_D,      DIR = IO, VEC = [0:7]
 PORT FPGA4_RDWR_B = FPGA4_RDWR_B, DIR = O
 PORT FPGA4_CS_B   = FPGA4_CS_B,   DIR = O
 PORT FPGA4_INIT_B = FPGA4_INIT_B, DIR = I
 PORT FPGA4_DONE   = FPGA4_DONE,   DIR = I
 PORT FPGA4_PROG_B = FPGA4_PROG_B, DIR = O

The following shows an example instantiation from a MHS file (an example can also be found in the XPS_Ctrlfpga_linux system that is contained in the BEE2 reference package).

BEGIN opb_selectmap
 PARAMETER INSTANCE   = opb_selectmap_0
 PARAMETER HW_VER     = 1.01.a
 PARAMETER C_BASEADDR = 0xe0002000
 PARAMETER C_HIGHADDR = 0xe00023ff
 BUS_INTERFACE SOPB   = opb
 PORT CCLK            = FPGA_CCLK
 PORT FPGA1_D         = FPGA1_D
 PORT FPGA1_RDWR_B    = FPGA1_RDWR_B
 PORT FPGA1_CS_B      = FPGA1_CS_B
 PORT FPGA1_INIT_B    = FPGA1_INIT_B
 PORT FPGA1_DONE      = FPGA1_DONE
 PORT FPGA1_PROG_B    = FPGA1_PROG_B
 PORT FPGA2_D         = FPGA2_D
 PORT FPGA2_RDWR_B    = FPGA2_RDWR_B
 PORT FPGA2_CS_B      = FPGA2_CS_B
 PORT FPGA2_INIT_B    = FPGA2_INIT_B
 PORT FPGA2_DONE      = FPGA2_DONE
 PORT FPGA2_PROG_B    = FPGA2_PROG_B
 PORT FPGA3_D         = FPGA3_D
 PORT FPGA3_RDWR_B    = FPGA3_RDWR_B
 PORT FPGA3_CS_B      = FPGA3_CS_B
 PORT FPGA3_INIT_B    = FPGA3_INIT_B
 PORT FPGA3_DONE      = FPGA3_DONE
 PORT FPGA3_PROG_B    = FPGA3_PROG_B
 PORT FPGA4_D         = FPGA4_D
 PORT FPGA4_RDWR_B    = FPGA4_RDWR_B
 PORT FPGA4_CS_B      = FPGA4_CS_B
 PORT FPGA4_INIT_B    = FPGA4_INIT_B
 PORT FPGA4_DONE      = FPGA4_DONE
 PORT FPGA4_PROG_B    = FPGA4_PROG_B
END

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Register Definition

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The core is controlled by two very simple registers, the data and control registers. The address map is defined below:

Control Register

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Controls the mode of the core (configure of FIFO), the state of the PROG_B pin, interrupt state, and the occupancy of the FIFOs when in FIFO mode.

Data Register

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Reads and writes to the data register result in either transfer of data from or to the SelectMAP interface.

In configure mode, writes to the data register will result in the transfer of the 8-bit value across the SelectMAP bus. During chip configuration all commands are sent to the chip as a series of four bytes to form a control word. Reads while in configure mode are currently not fully supported, although they have been in the past (version 1.00a).

In FIFO mode, writes to the data register will cause the byte to be written to the user FPGA write FIFO. Before all writes you should check the Write FIFO Count (WFC) field in the control register to make sure that you do not overflow the FIFO. The count will give the number of bytes that can currently be written into the FIFO, so it is safe to write up to that count without polling the control register again. If you do overflow the FIFO, the overflowed bytes will be lost. A read of the data register will result in a single byte being pulled from the read FIFO on the user FPGA. Before doing any reads while in FIFO mode, you must check the Read FIFO Count (RFC) field of the control register to make sure it is safe to read. The RFC will tell you how many bytes are currently in the FIFO and it is safe to read up to that count without polling. Underflowing the FIFO can potentially lock up the OPB bus and deadlock the system in the current design, so it is crucial to check the RFC before reading.

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Interrupt Behavior

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The opb_selectmap core provides independent access to each user FPGA SelectMAP bus. Therefore, the core exports four independent interrupt requests. Interrupts can only become active when in FIFO mode and are edge triggered. The user FPGA FIFO core triggers an interrupt by asserting the INIT_B pin (the opb_selectmap_fifo core has several different interrupt behaviors, see the documentation for more details). The interrupt will remain asserted until the IRQ bit in the control register is cleared by the ISR.

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Drivers

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There are currently two drivers available for the opb_selectmap core. First, the core is used both for configuration and for communication in the BORPH/Linux operating system. For more information on BORPH please visit the home page.

The second driver is a Linux character device driver which gives simple, scriptable access to the device. The driver is currently included in the default BEE2 Linux tree and the default kernel configuration (you can view the source CVSweb).

The driver exports two interfaces to the user. First, a simple proc entry is created for each device with the names /proc/fpga/selectmap[1-4]. Reading the proc entry gives the current status of the device, such as the mode and the state of the PROG_B and DONE pins. Users can write an ascii string to the proc entry with the side effect of writing that value to the control register for that FPGA. For example, to set the mode of to configure you could execute the following command:

$ echo 0f000000 > /proc/fpga/selectmap1

The second driver interface is a character device entry created for each device with the names /dev/selectmap[1-4]. This is the primary way of interacting with the core in both configuration and FIFO mode. The character device interface has the same semantics of almost any other file, except that it does not support certain operations such as seek. Interacting with the device is as simple as first opening the /dev file and then performing reads and writes. Configuration of a chip is made very easy, as you can simply use the tools cat and echo to program a chip. For example, here is a very simple set of commands to program a user FPGA:

$ echo 00000000 > /proc/fpga/selectmap1  # Assert PROG_B to deprogram FPGA
$ echo 04000000 > /proc/fpga/selectmap1  # Deassert PROG_B and set to Configure mode
$ cat download.bit > /dev/selectmap1     # Send the bitstream
$ echo 0f000000 > /proc/fpga/selectmap1  # Set FIFO mode (if desired)

One thing to note is that the Linux driver is not very sophisticated (it is intended as a debug driver) and thus is not very high performance. For example, it does not take advantage of the interrupt signals and performs all I/O as programmed I/O. If you are planning to use the FIFO mode capabilities in a high performance application you will either need to implement this functionality or borrow from the BORPH driver which takes advantage of interrupt driven I/O and performs better OS buffer management.

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Frequently Asked Questions

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None so far.

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Core Facts

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Revision History

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Click the Info link below to see the revision history.