BEE2 IP Core Documentation
General Cores
Memory System
(ddr2_controller_v2_00_a) - Low-level DDR2 controller with bank management. BEE2Memory
(async_ddr_v2_00_a) - Asynchronous command FIFOs providing user memory interface.
(plb_ddr2_v2_00_a) - PLB attachment for user memory interface.
(multiport_ddr2_v2_00_a) - Multi-port arbiter for user memory interface.
Communication
(interchip_block_v1_00_a) - Low-level, board synchronous interchip communication.
(XAUI_interface_v2_00_a) - XAUI communication core.
(opb_fifo_v1_00_a) - General purpose communication FIFOs.
Control FPGA Cores
Display
(opb_framebuffer_v2_00_a) - DVI frame-buffer with OPB control attachment.
Configuration
(opb_selectmap_v1_01_a) - SelectMAP core for user FPGA programming and communication. Bee2CoreOpbSelectMap
IIC
(opb_software_iic_v1_00_a) - Software IIC (bit banging) controller.
User FPGA Cores
Communication
(opb_selectmap_fifo_v1_01_a) - FIFO based data transfer using SelectMAP interface
BEE2 Core Documentation Template: Bee2CoreTemplate