BEE2 Errata

This page is intended to collect various bits of information regarding the use of the BEE2 board and its gateware infrastructure. Please scan through this page before working on your own designs, and please consult it first if you have strange errors with your designs. If you come across any tips, tricks, or vital information that should be easy to find, please feel free to add it to this page.

  1. BEE2 Errata
    1. Replacing SystemACE oscillator
    2. No output on RS232 serial or JTAG problems
    3. Linux on control FPGA stops booting when programming with JTAG
    4. User FPGA JTAG chain problems
    5. User FPGA startup clock
    6. User FPGA designs without SelectMAP block

Replacing SystemACE oscillator


Due to the length of the JTAG chain that connects the SystemACE chip to the control FPGA, there have been some problems booting the control FPGA with certain bitstreams. This problem manifests itself as the SystemACE status LED turning red during initial programming, or by software not properly starting on the embedded PowerPC (i.e. Linux bootloader not showing up).

The problem is caused by the oscillator that is installed on all BEE2's with a serial number lower than 2.2.X. The oscillator installed on those boards is a 32MHz oscillator that drives the SystemACE too fast for the JTAG chain. In all boards after the 2.2.X batch, this problem has been fixed. For boards before that, you will need to install a new 16MHz oscillator, or verify that your board has already been updated. Most sites with boards will receive a new oscillator in the mail from BWRC.


The oscillator to be replaced is located under the CompactFlash card holder next to the SystemACE chip.

The oscillator has four surface mount pads that must be desoldered and lifted from the board. We suggest using two paddle iron tips, or using a single tip and some solder wick to lift the old oscillator. When the old oscillator has been removed, clean up the pads with some solder wick.

Finally, apply solder paste or solid solder to attach new oscilator. The picture below shows the correct orientation.

To test the correctness of the replacement, simply power on the BEE2 without a CompactFlash card in the slot. You should see the SystemACE status LED blink red at a slower pace than usual. Next, insert the BEE2 test suite on a CF card and make sure it properly boots and runs. Finally, insert a CF with the default Linux base system and make sure that too boots and runs.

No output on RS232 serial or JTAG problems

Designs on the control FPGA that use DDR2 DIMMs must have a DIMM inserted into each bank that is used (i.e. has a memory controller driving it). If you do not have a DIMM in the slot then the unterminated reflections of signals sent to the DIMM can cause problems with the RS232 and JTAG lines.

For any design that instantiates a DDR2 controller on a bank, that bank must have a DIMM inserted.

Linux on control FPGA stops booting when programming with JTAG

If you are having trouble with Linux freezing up in the boot process, it is likely because you don't have a CompactFlash card in the CF holder.

If the Linux kernel contains the SystemACE driver, then regardless of whether you programmed the control FPGA with JTAG or from the SystemACE, you need to have a CompactFlash card in the CF holder for the kernel to boot because the SystemACE driver will block trying to read the card.

User FPGA JTAG chain problems

Due to the length of the JTAG chain that connects the four user FPGAs, we have sometimes observed instability in both programming the FPGAs via JTAG and when performing debugging with Chipscope or XMD. The simplest solution to this problem is to simply instruct the debugging tools (Impact, Chipscope, or XMD) to use the JTAG cable at a slower speed.

For example, if you are using a Xilinx Parallel IV cable, the fastest setting is 5 MHz with ECP mode. If you experience problems when running at this speed, you can simply disable ECP mode and the cable will drop to 200 KHz. At this lower speed we have not experienced any problems in the lab.

User FPGA startup clock

For user FPGA designs that are programmed via the SelectMAP interface from the control FPGA, the proper startup clock must be selected in the bitgen options. The bitgen options are set via the etc/bitgen.ut file in a XPS project.

The two clocks that are of primary interest are the JTAG and CCLK clocks. When programming the FPGA from the JTAG chain you want to select the JTAG clock. The bitgen option is as follows:

-g StartUpClk:JtagCLK

To configure the user FPGAs with the SelectMAP interface from the control FPGA you must select CCLK. The bitgen option for this is:

-g StartUpClk:Cclk

For more information about the bitgen options you can refer to the Development System Reference Guide.

User FPGA designs without SelectMAP block

When creating an user FPGA design that does not instantiate a SelectMAP block (opb_selectmap_fifo or others), you must instantiate a place holder core that will drive the SelectMAP pins to a safe state. If you don't do this the pins will change to unconnected I/Os that can lock up the control FPGA and cause other strange errors. An example of this can be found in the user FPGA design in the "MPI demo" on the Bee2Reference page.

If you do this, please be careful not to send any data through the SelectMAP character device on the control FPGA as it could potentially mess up the state of the user FPGA.

Bee2Errata (last edited 2006-07-12 21:36:25 by alschult)