In order to use the external peripherals connected to the BEE2 FPGAs, you will need to know the external pin assignment. Fortunately, many of the cores provided in the BEE2 infrastructure package contain the pin information within the cores themselves, which means that using these cores is as simple as dropping them into your design. However, some of the cores require external pin assignment via a UCF file, and there may be times when a user wants access to the external pins directly. In the former case, the easiest way to get the UCF constraints is to view the UCF files contained within our reference examples (see Bee2Reference). In the latter case, we have provided an Excel file that can easily be searched to determine pin information. This document gives a very brief overview of how to find and use this pin database.
Pin Assignment Spreadsheet
All pin assignments for both user FPGAs and the control FPGA can be found in our pin assignment spreadsheet Pin_assign.xls
In the spreadsheet the pin assignments can be found on the sheets labeled ctrlFPGA for the control FPGA and usrFPGA for the user FPGA. The following is an example of what the ctrlFPGA sheet looks like:
The key parts of the spread sheet are the following columns:
Pin column gives the actual pin location for the listed feature. This can be directly plugged into a LOC constraint in a UCF file or in HDL.
IOB column gives the actual name of the IOB. This is useful for checking that constraints like 1 clock per pair are met (this is a problem that comes up in some of the inter-chip LVCMOS traces).
Signal column gives the name of the net attached to that external pin. These names aren't necessarily the name of the net in a user design, but rather the schematic name. These are generally descriptive enough to describe the resource.