IBOB Board FAQ
- IBOB Board FAQ
- Frequently Asked Questions
- What is naming nomenclature of ADC ports ?
- Can the CX4 connector at the non-iBOB end of a CX4 link have chassis ground connected to digital ground ?
- What is the acceptable reference frequency range for the non-iBOB end of a CX4 link? Is it 156.25 MHz +/- 0.01%? Can the link run with one end using 156.24 MHz ?
- I'm using Pierre's XAUI_interface_v1_00 pcore. What do I need to know about the clock frequencies and data rates of the inputs and outputs ?
- How full is the fifo when rx_almost_full goes active ?
- How big is the fifo ?
- If I have the same app_clk on both ends and it's substantially less than 156.25 MHz, can I tie rx_get and tx_valid to '1' and ignore (i.e. leave open) rx_almost_full, rx_valid, rx_empty, and tx_full? Would this effectively give the appearance of a fully synchronous connection with some unknown (but measurable) latency ?
- If I use the xaui_if.ngc file from mlib_devel, will I have to synthesize/map/par/bitgen on beehive ?
- Why does this pcore's transceiver.vhd file have "-- synthesis translate_off" and "-- synthesis translate_on" around the gt_xaui_2's generic map? Did Core Generator create it that way ?
- How do I program the PROM on the IBOB for automatic startup?
Other useful FAQs:
The ADC board FAQ - AdcFaq
The MSSGE FAQ - MssgeFaq
The BEE2 board FAQ - Bee2Faq
Block Creators FAQ - BcFaq
Frequently Asked Questions
What is naming nomenclature of ADC ports ?
The ADC closer to the iBOB power connector (J23 on iBOB) is named adc1 and the one further away (J22 on iBOB) is adc0.
This does not present any problem, as the chassis ground on the iBOB CX4 connector is left floating. However, make sure you use the digital ground and not a filtered ground, such as an analog ground or the MGTs ground, because the cable is going to act as an antenna and inject a lot of noise in this ground plane.
The V2P datasheet states +- 100ppm mismatch (or +-0.01%), and the crystal on the iBOB is +-50ppm. It leaves 50ppm margin, and 156.24 is at 60ppm. So theorically it doesn't work, but practically I think it could do. It's worth trying ...
The non-MGT ports are on the other side of an async fifo clocked by app_clk and can run at any clock rate.
App_clk can be anything.
A good abstraction for the XAUI link would be an asyncronous FIFO with each side on a different board. The only thing that matters is the rate at which you put/get stuff in/from the FIFOs. If you are putting valid samples in the link every cycle and get a sample every cycle, then you should make sure that you have the same clock on the two sides. But if you don't put samples in the link every cycle, or don't expect a sample every cycle, then the two app_clk can be different.
The mgt_clk should be a 156.25 Mhz signal comming directly from an ibufgds, with nothing inbetween the buffer and the core. It should be comming from very specific IO pins on the FPGA: the BREFCLK that correspond to the side of the FPGA your MGTs are on.
How full is the fifo when rx_almost_full goes active ?
How big is the fifo ?
If I use the xaui_if.ngc file from mlib_devel, will I have to synthesize/map/par/bitgen on beehive ?
How do I program the PROM on the IBOB for automatic startup?
Check out the file http://seti.ssl.berkeley.edu/casper/memos/ibob_prom_proc.pdf
Local copy (1/2/07): attachment:ibob_prom_proc.pdf