|
IBM |
Freescale |
Leon3 |
OpenSPARC T1 (Niagara) |
Simply RISC S1 |
QEMU/FAST functional |
MicroBlaze (v5.0) |
|
ISA |
PPC405 |
PPC |
SPARC V8 |
UltraSPARC Arch 2005 (SPARC V9+) |
SPARC V9 |
UltraSPARC Arch 2005 (SPARC V9+) |
x86 |
MIPS-like RISC (w/o MMU) |
FPU |
no |
no (available) |
Yes (no source code) |
Yes |
not yet |
Yes |
software |
partial IEEE 754 single precision |
microarchitecture |
5-stage, in-order, single-issue |
7-stage, in-order? |
7-stage, in-order pipeline |
8-core, 32-thread, 6-stage pipe (1 core/1 thread in initial FPGA version) |
ISA only |
1-core, 4-thread derivative of OpenSPARC T1 |
ISA |
3-stage in-order |
licensing |
restricted |
yes |
LGPL |
GPL |
SIMICS |
GPL |
LGPL |
Xilinx EDK |
speed |
30MHz |
25MHz |
50MHz (0.85 MIPS/MHz) |
25 MHz (Virtex-II) |
<10MIPS |
_?_ |
5MIPS |
>100 MHz (0.5 MIPS/MHz) |
size, in 4-input LUTs (w/o FPU) |
20K |
33.5K |
8K |
135K (full 8-Core), 48K (1 thread/1 core, placed&routed) |
13K (partial core) |
_?_ |
PowerPC |
2.8K |
HDL |
Verilog |
Verilog |
VHDL |
Verilog |
Bluespec |
Verilog |
Verilog |
Encrypted VHDL |
verification suite |
no |
no |
yes |
Niagara (OpenSPARC) |
Niagara |
Niagara (OpenSPARC) |
no |
no |
application base |
ok |
ok |
ok |
ok |
Solaris Apps |
_?_ |
everything |
poor |
operating system(s) |
ok |
ok |
Linux 2.6 |
Solaris, Linux, *BSD |
Solaris |
Solaris, Linux, *BSD |
Windows, Linux, Solaris, ... |
uClinux 2.4 |
hardcore |
yes |
yes |
no |
no |
no |
no |
no |
no |
64 bit |
no |
no |
no |
yes, full 64-bit |
yes |
yes, full 64-bit |
yes (speed) |
no |
SMP support |
no |
no |
Snoopy (w/o MMU) |
CMT |
not yet |
CMT |
_?_ |
no |
virtualizability |
no |
no |
no |
yes (Hypervisor, LDOMs) |
no |
yes? (via Hypervisor) |
_?_ |
no |
bus interface |
64-bit PLB |
64-bit AMBA AHB2.0v6 |
32-bit AMBA (64-bit soon) |
128-bit |
64-bit (virtualized) |
Opencores wishbone |
_?_ |
32-bit OPB/MCH |
Leon3 report on Virtex-2 and Virtex-5 (section 1.3 and 1.4) - http://radlab.cs.berkeley.edu/wiki/LEON3_area
ProtoFlex-SPARC follows a hybrid execution model that splits execution between FPGA emulation (a subset of the functionality) and SIMICS software simulation.